Yasushi Ooi

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking

A 1.5-W single-chip MPEG-2 MP@ML real-time video encoder large scale integrated circuit (LSI) has been developed. To form an MPEG-2 encoder system, we employ two 16-Mb synchronous DRAMs, a microprocessor unit (MPU), and an audio encoder LSI. Owing to a two-step hierarchical search scheme and a novel adaptive search window scheme, the search range of motion estimation is -48/+47 horizontal and -96/+15.5 vertical, and the pseudo search range, which is the size when the location of the search window is adaptively shifted, is -96/+95 horizontal and -32/+31.5 vertical. We have also developed low-power clocking techniques, i.e., demand-clock controller, local-clock controller, and low-power flip-flops, which can eliminate waste of power in clocking. We have successfully fabricated these new designs as a low-power single-chip MPEG-2 encoder LSI. The operating frequency except for a synchronous DRAM interface unit and a video in/out unit is 54 MHz. The supply voltage to the first and second search engines in a motion estimation unit can be successfully lowered to 2.5 V and the others are 3.3 V. Into a 12.45/spl times/12.45 mm/sup 2/ chip with 0.35-/spl mu/m CMOS and triple-metal layer technology are integrated 3.1 M transistors.

An encoder/decoder chip set for the MPEG video standard

A VLSI chip set capable of real-time MPEG (Moving Picture Experts Group) video encoding/decoding has been developed. It is composed of an inter-frame prediction chip, a transform and quantization chip, and a variable length coding chip. To make the chip set more cost effective, the MPEG algorithms are first partitioned into three blocks on the basis of their characteristics. Individual chip architectures are designed with the use of programmable DSP and application specific array approaches. A hierarchical data transmission method is introduced for use among the chips and frame memories. By using three chips, an MPEG video encounter can compress a 30-frames/s image sequence of 352 pels*240 lines. A decoder can be constructed with two chips for the same sequence.<<ETX>>

A 162 Mbit/s variable length decoding circuit using an adaptive tree search technique

A high-speed Huffman decoder for real-time video applications has been developed. The most dominant part of MPEG video bit-stream, DCT coefficients, can be decoded in 4 cycles or less using the proposed circuit, while the table size is smaller than the case of the conventional binary search. Bit-streams can be decoded up to 6 bit/cycle, which enables 162 Mbit/s decoding at 27 MHz.<<ETX>>

A scene-adaptive one-pass variable bit rate video coding method for storage media

This paper proposes a one-pass VBR (Variable Bit Rate) video coding method that maintains the stability of its quantization scale by using a large size virtual buffer to smooth out the difference between a generated bit count and a target bit count. To improve video quality, the quantization scale is adjusted according to the coding complexity of scenes. Experimental results show that the standard deviations of quantization scale distributions are only 30/spl sim/40% of those produced by CBR (Constant Bit Rate) coding, where averaged quantization scale values are roughly the same as those of CBR. The worst quality periods defined as the duration that the quantization scale exceeds a certain level are reduced from 28.7% to 7.8% in total coding time at 4 Mbps coding. The method can be applied to real-time video recording applications.

An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU

This paper describes an MPEG-2 encoder architecture based on a hard-wired LSI with a control MPU. All basic functions of MPEG-2 MP@ML video compression are integrated in the dedicated LSI. For the motion estimation, a horizontally subsampled, diamond search was employed as a simplified first search step. It can reduce operations to 20% of the full-search, with an estimated SNR degradation of only -0.1 dB. To help achieve a single-memory interface, a pair of 81 MHz, 16 Mb SDRAMs are used as a frame buffer and a code buffer. Data bandwidth between the SDRAMs and the LSI is kept to less than 94% of the maximum data rate. Jobs assigned to the control MPU need be executed less frequently than those of the macroblock coding, which helps reduce the requirements for MPU performance to about 7 MIPS.

A block processing unit in a single-chip MPEG-2 video encoder LSI

This paper describes a block processing unit in a single-chip MPEG-2 MP@ML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 μm triple-layer metal CMOS cell-base technology at 54 MHz.

A compact motion estimator with a simplified vector search strategy maintaining encoded picture quality

A compact motion estimator employing a simplified two-step full-search strategy has been proposed. In the first step, 2-pel precision motion vectors are obtained using 4-to-1 subsampling with a LPF. In the second step, half-pel precision vectors are obtained. The strategy reduces the number of operations and memory access cycles to 1/11 and 1/2, respectively, while maintaining encoded picture quality within 0.2 dB differences in SNRs. Using this estimator, a bidirectional motion compensation LSI with a -16.0/+15.5 pels search range has been developed for real-time MPEG1 video encoding.