Hideo Yoshino

Evaluation of interface potential barrier heights between ultrathin silicon oxides and silicon

Interface potential barrier heights for ultrathin silicon oxides (15– 44 A) on silicon and effective electron masses in some of these oxides are evaluated. Evaluation is performed using a new technique of analyzing the charging characteristics of metal‐nitride‐oxide‐semiconductor capacitors. Oxides thicker than 36 A have the same potential barrier heights as those for thick oxides, assuming the effective electron mass of the oxides is the same. However, for oxides thinner than 31 A, the potential barrier heights decrease and the effective electron masses increase as the oxide thickness decreases. These results suggest that oxides at least thicker than 36 A can be applied to metal‐oxide‐semiconductor field‐effect transistors as gate oxides.

A high-performance self-aligned UMOSFET with a vertical trench contact structure

We compare the electrical characteristics of a UMOSFET having a trench contact (TC-UMOS) for the source and the body regions with those of the conventional surface contact UMOSFET (SC-UMOS). For SC-UMOS, there exists an optimum cell pitch which gives the lowest on-resistance. Reducing the cell pitch beyond that point results in increased on-resistance because the source contact resistance increases as the cell pitch is further reduced. On the contrary, for TC-UMOS, the on-resistance decreases as the cell pitch is reduced because the source contact resistance does not change, These results show that TC-UMOS is more effective than SC-UMOS for reducing the on-resistance by scaling down of the cell pitch. The minimum specific on-resistance of TC-UMOS is 0.43 m/spl Omega//spl middot/cm/sup 2/. Furthermore, the critical avalanche current of TC-UMOS is enhanced significantly compared with that of SC-UMOS because the base resistance of the parasitic npn-bipolar transistor of TC-UMOS is lower than that of SC-UMOS. >

New model of electron free path in multiple layers for Monte Carlo simulation

A new model of an electron free path in multiple layers is proposed for Monte Carlo simulation of electron trajectories. In this model, the free path is calculated taking into account not only the scattering probability in the layer involving the initial scattering point but also that in the layers along the scattering direction. The result, simulated with the new model, agrees with the experimental result much better than results obtained with conventional models for backscattered electron intensity. It is also suggested that the simulation accuracy for the electron beam lithography is improved using the new model.

Device simulation of a thin-film silicon on insulator power metal-oxide-semiconductor field-effect transistor for structure optimization

This paper proposes an optimised device structure based on the results of numerically simulating thin-film silicon on insulator (SOI) power metal-oxide-semiconductor field-effect transistors (MOSFETs) in the 50-V class. The dependence of the breakdown voltage and specific on-resistance on the doping concentration of the drain offset region, on the thickness of the superficiai silicon layer, on the thickness of the buried oxide layer, and on the drain offset length are compared for buried channel MOSFETs and surface channel MOSFETs.

Effect of Platinum Particles in Dual SiO2 Interface on Charge Storage Properties

The charge storage properties of the Metal-Oxide-Metal particles-Oxide-Semiconductor structure, in which charge storage traps are introduced by interposing metal particles between CVD SiO2. and thermally grown SiO2, have been investigated. As metal particles, Pt evaporated by electron beam has been used. The distinct effect of Pt particles on the charge storage properties has been observed, compared to the properties of the Metal-Oxide-Oxide-Semiconductor structure. The amount of the flat-band voltage shift and the retention time are changed with the heat treatment condition in the O2 atmosphere after the CVD SiO2 deposition upon metal particles. This is explained by the growth of SiO2 on Si by the heat treatment in O2, which is clarified by structural analysis by means of Auger electron spectroscopy.

Passivation of Sodium Ions in Metal Oxide Semiconductor Structures by Annealing with Ultraviolet Light

The passivation effect of ultraviolet light annealing on sodium-contaminated metal oxide semiconductor (MOS) devices was studied. MOS devices were intentionally contaminated with sodium during the interconnect formation process after the gate electrode was formed. After aluminum pad formation, these devices were irradiated with ultraviolet light (wavelength 250 to 370 nm) at elevated temperatures. Sodium-induced threshold voltage of active and parasitic MOS transistors returned to original values during the annealing. It is assumed that positive sodium ions in the oxides are neutralized with electrons excited by ultraviolet light. This passivation effect becomes more prominent as the temperature becomes higher, suggesting that the diffusion of sodium ions in the oxides is closely related to the passivation effect. A model for this temperature-dependent passivation effect is presented. Bias-temperature testing revealed that this passivation effect is remarkably stable for 100 h even at 200°C.

Absorption Saturation Energy Density of InGaAs-InAlAs Multiple Quantum Well under Tensile and Compressive Strain

Optical absorption saturation density Is was measured for InxGa1-xAs-In0.52Al0.48As multiple quantum well structures grown on InP (100) substrates by molecular beam epitaxy. Indium composition x was varied from 0.32 to 0.70 so that the quantum well layer was under tensile strain (x 0.53). Optical measurement was carried out using femtosecond light pulses from the optical parametric amplifier of a mode-locked Ti-sapphire laser amplifier. The density Is in a sample changed as a function of photon energy and exhibited a minimum value at the band-edge exciton energy. This minimum Is showed the smallest value at x=0.46 (under tensile strain) of all the samples with different x. This was in marked contrast to the results reported in the literature. Degenerate pump-probe measurement was also carried out, and the results showed that the relative transmission change ΔT/T measured at zero delay between the pump and probe pulses exhibited the largest value at x=0.46, confirming the result of Is measurement.

MOS LSI Fabrication Process using Direct Electron Beam Writing

A procedure to construct an MOS LSI fabrication process, using direct electron beam writing technology, has been proposed. Positive resist PMMA and aluminum liftoff technique are used. Proximity effect and resist thickness dependence, as well as line width and undercut profile of resist patterns, play important roles in determination of optimum patterning condition. Electron beam radiation damage can be annealed out by suitable heat-treatment, while the amount of damage depends on processing steps. The process also includes a plasma etching with improved gas composition, a two-step glass flow technique and molybdenum wet etching with newly developed solution. Successful fabrication results, 1-kbit MOS RAM and TEG with 2 µm minimum pattern dimension, demonstrate the validity of these processes.