Kazuhide Kiuchi

A fault-tolerant 256K RAM fabricated with molybdenum-polysilicon technology

Describes a 256K molybdenum-polysilicon (Mo-poly) gate dynamic MOS RAM using a single transistor cell. Circuit technologies, including a capacitive-coupled sense-refresh amplifier and a redundant circuitry, enable the achievement of high performance in combination with Mo-poly technology. Electron-beam direct writing and dry etching technologies are fully utilized to make 1 /spl mu/m accurate patterns. The 256K word/spl times/1 bit device is fabricated on a 5.83 mm/spl times/5.90 mm chip. Cell size is 8.05 /spl mu/m/spl times/8.60 /spl mu/m. The additional 4K spare cells and the associated circuits, in which newly developed electrically programmable elements are used, occupy less than 10 percent of the whole chip area. The measured access time is 160 ns under V/SUB DD/=5 V condition.

A 256K RAM fabricated with molybdenum-polysilicon technology

128K block has two arrays of 64Kb fundamental cells and about 2Kb spare cells, and dummy sense circuit’. The spare cells are connected with four pairs of spare bit-lines and two spare word-lines. Since each pair of spare bit-lines require one additional sense amplifier, one block bas 516 amplifiers. The amplifier includes coupling capacitors, which make it possible to obtain a high refresh voltage. Amplifier circuits and operating waveforms are shown in Figure 2. The amplifier begins to detect the signal by clock @ ~ 1 , and amplification is accelerated by clock @ ~ 2 . After sensing operation the capacitors are connected with the bit-lines by clock @B. Therefore the potential of the bit-line becomes high enough for refreshing. Clock @ ~ 1 also drives the coupling capacitors. During sensing period, however, the capacitors are separated from the bitlines to prevent an increase in bit-line capacitance. As a result, this amplifier can detect a signal of ? 50mV. In the memory cell array the word line crosses over the storage capacitor electrodes, and is composed of molybdenum, which is the gate material of the cell transistor2. The bit-line is made of interconnection metal of aluminum and the storage capacitor electrode consists of polysilicon. The memory cell has been designed to obtain the signal of * 120mV in the worst case. Since both the word-line and bit-line materials are metallic, the propagation delay in the array becomes small. In other circuits Si-gate transistors are used. To improve the yield of RAMS the fault-tolerant concept is introduced. Spare cells can substitute for defective cells. This substitution is achieved by utilizing electrically programmable polysilieon resistors, which include PN junctions. Figure 3 shows the spare column decoder using these resistors. The resistance is at least 109Q initially, and it becomes less than 3 x l O 3 Q after transition. Since the resistor has low transition voltage and current (11V and 7mA), programming is controlled easily by MOS circuits. The substitution requires only 15V programming pulses and can be done during wafer probing. The resistor characteristic is shown in Figure 4. To program the A block diagram of the circuit is shown in Figure 1. Each

A New Self-Aligned Framed Mask Method for Selective Oxidation

A new selective oxidation method, which realizes fine isolation width for MOS LSIs, has been developed. The oxidation mask in this method has a Si3N4 frame formed at a perimeter of a conventional mask pattern by self-aligned technique. This technique is composed of deposition step of Si3N4 film to cover the conventional mask and dry etching step of this film to form the frame without a photoresist pattern. Birds beak extent is suppressed to less than 300 nm. Dislocation generation in silicon substrate is also suppressed in this framed mask method. Birds beak suppression brings about extention in an effective device area and realizes a transistor with effective channel width 1.0 µm wider than that in the conventional mask method. The p-n junction prepared by this new method exhibits as small leakage current as that by the conventional method.

A 65 mW 128K EB-ROM

A low power read-only memory (128K EB-ROM) has been developed using direct electron-beam data writing and 2 /spl mu/m VLSI fabrication technology. Programming of information in the ROM is accomplished by selective use of a field oxide in place of a thin gate oxide. The memory cell array is divided into eight current discharge (CD) units. Only one of the eight CD units, which contains a selected cell, is activated by the 3-bit extra decoder. The large capacitance enlarged by the Miller effect is markedly reduced. Moreover, the total capacitance to be precharged is also reduced. High performance output buffer circuitry is adopted, which has a high logic threshold voltage. As a result, the fabricated 128K EB-ROM is capable of 65 mW power dissipation under 400 ns cycle time and 5 V DC supply voltage conditions and 200 ns access time. Memory cell and chip dimensions are 8 /spl mu/m/spl times/7.75/spl mu/m and 3.75 mm/spl times/5.5 mm, respectively.

Direct Electron Beam Data Writing Technology for 128K EB-ROM

A 128 K-bit MOS read-only memory has been developed using direct electron beam data writing technology. The technology has been applied, using 1) scanning electron beam exposure system with high registration accuracy, 2) advanced wafer processes to fit the EB lithography, and 3) highly sensitive positive resist, FPM. Programming of information in the ROM is accomplished by modifying threshold voltage of transistors, where field oxide is used as a gate oxide in place of thin gate oxide. Through the present EB lithography, the alignment accuracy of ±0.15 µm and the resist pattern size accuracy of ±0.15 µm are obtained. The cell size and chip size of the ROM are 8 µm ×7.75 µm and 3.75 mm ×5.5 mm, respectively. The fabricated EB-ROM is capable fo 200 ns access time and 65 mW power dissipation for a single supply voltage of 5 V and is loaded with Chinese character patterns.

Invited) A 64K MOS RAM Design

A 64-kbit, low power MOS RAM, composed of 2µm channel MOS transistors, has been developed. At first, analysis with sense circuit was made and the relation between sensitivity and factors which affect sensitivity was clarified. According to the guide lines obtained from the relation, development of a new sense circuit and design method for the sense circuit were made. It has been verified that the sense circuit can detect a signal smaller than ±30 mV through the fabrication of a 1K RAM. A new level detecting circuit, having a logic threshold voltage independent of MOS transistor threshold voltage, has been developed. The circuit gives a large margin to TTL interface circuits in LSI. The 64K characteristics are 200 ns access time, 500 ns cycle time and 150 mW power consumption under typical voltage conditions; 7V (VDD) and -2V (VBB).

A 1-/spl mu/m Mo-Poly 64-Kbit MOS RAM

This paper describes a 1-m 64-kbit MOS RAM using Mo-poly technology. New 1-/spl mu/ m double-gate technology using molybdenum and polysilicon (Mo-poly technology) is proposed. In this technology, molybdenum and polysilicon are used for word lines and storage capacitor electrodes in the memory cell, respectively. Therefore, the propagation delay in a word line becomes extremely small and memory cell size is reduced. New two step annealing was developed for stabilizing an Mo-gate MOS structure. Design is optimized for 1-/spl mu/ m Si-gate FETs in peripheral circuitry. A 1-/spl mu/ m Mo-poly 64-kbit MOS RAM was experimentally fabricated by using 1/spl mu/ m process technologies. The cell size and die size were 8 /spl mu/ m X 8 /spl mu/ m and 3 mm X 3 mm, respectively. Access time was less than 100 ns.