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Featured researches published by Hidetoshi Sato.


Proceedings of SPIE, the International Society for Optical Engineering | 2007

New method of Contour based mask shape compiler

Ryoichi Matsuoka; Akiyuki Sugiyama; Akira Onizawa; Hidetoshi Sato; Yasutaka Toyoda

We have developed a new method of accurately profiling a mask shape by utilizing a Mask CD-SEM. The method is intended to realize high accuracy, stability and reproducibility of the Mask CD-SEM adopting an edge detection algorithm as the key technology used in CD-SEM for high accuracy CD measurement. In comparison with a conventional image processing method for contour profiling, it is possible to create the profiles with much higher accuracy which is comparable with CD-SEM for semiconductor device CD measurement. In this report, we will introduce the algorithm in general, the experimental results and the application in practice. As shrinkage of design rule for semiconductor device has further advanced, an aggressive OPC (Optical Proximity Correction) is indispensable in RET (Resolution Enhancement Technology). From the view point of DFM (Design for Manufacturability), a dramatic increase of data processing cost for advanced MDP (Mask Data Preparation) for instance and surge of mask making cost have become a big concern to the device manufacturers. In a sense, it is a trade-off between the high accuracy RET and the mask production cost, while it gives a significant impact on the semiconductor market centered around the mask business. To cope with the problem, we propose the best method for a DFM solution in which two dimensional data are extracted for an error free practical simulation by precise reproduction of a real mask shape in addition to the mask data simulation. The flow centering around the design data is fully automated and provides an environment where optimization and verification for fully automated model calibration with much less error is available. It also allows complete consolidation of input and output functions with an EDA system by constructing a design data oriented system structure. This method therefore is regarded as a strategic DFM approach in the semiconductor metrology.


Photomask and next-generation lithography mask technology. Conference | 2003

Technological capability and future enhanced performance of HL-7000M

Masaomi Tanaka; Suyo Asai; Hajime Kawano; Ken Iizumi; Kazuyoshi Oonuki; Hiroyoshi Takahashi; Hidetoshi Sato; Rikio Tomiyoshi; Kazui Mizuno; Genya Matsuoka; Hiroya Ohta

HL-7000M electron beam lithography system has been developed as a state-of-the-art reticle writer for the generation of 90nm node production and 65nm node development. It is capable of handling relatively large volume data files such as full Optical Proximity Correction patterns and angled patterns for System on Chip. Aiming at technological requirements, a newly designed electron optics column generating a vector-scan variable shaped beam and a digital disposition system with a storage area network technology have been integrated into HL-7000M. Since the requirement on the critical dimension uniformity is extremely demanding on the ITRS roadmap, HL-7000M has also needed to improve its beam shaping performance. The ability relevant to shaping beam size has a great impact on its line width or critical dimension accuracy. To reduce an aberration caused within the shaping lens system, the dual quadrupole electrostatic shaping deflector has been utilized. By applying advanced technologies, HL-7000M with a result of critical dimension uniformity (2.5nm and 2.8nm in 3σ) has achieved meeting its target requirement of the 90nm generation for production. Additionally HL-7000M has proved its potential, allowing the industry to establish quickly the processes further beyond the requirements of the 65nm node for development.


Proceedings of SPIE | 2009

New approach for mask-wafer measurement by design-based metrology integration system

Hiroaki Mito; Katsuya Hayano; Tatsuya Maeda; Hiroshi Mohri; Hidetoshi Sato; Ryoichi Matsuoka; Shigeki Sukegawa

OPC technique is getting more complicated toward 32nm and below technology node, i.e. from moderate OPC to aggressive OPC. Also, various types of phase shift mask have been introduced, and then the manufacturing process of them is complicated now. In order to shorten TAT (Turn around time) time, mask technique need be considered in addition to lithography technique. Furthermore, the lens aberration of the exposure system is getting smaller, so the current performance of it is very close to the ideal. On the other hand, when down sizing goes down to 32nm technology node, it starts to be reported that there are cases that size cannot be matched between a mask pattern and the corresponding printed pattern. Therefore, it is very indispensable to understand the pattern sizes correlation between a mask and the corresponding printed wafer in order to improve the accuracy and the quality, in the situation that the device size is so small that low k1 lithography had been developed and widely used in a production. Then it is thought that it is one of the approaches to improve an estimated accuracy of lithography by using contour that was extracted from mask SEM image in addition to mask model. This paper describes a newly developed integration system in order to solve issues above, and the applications. This is a system which integrates CG4500; CD-SEM for mask and CG4000; CD SEM for wafer; using DesignGauge; OPC evaluation system by Hitachi High-Technologies. It was investigated that a measurement accuracy improvement by executing a mask-wafer same point measurement with same measurement algorithm utilizing the new system. At first, we measured patterns described on a mask and verified the validity based on a measurement value, picture, measurement parameter and the coordinate. Then create a job file for a wafer CD-SEM using the system so as to measure the same patterns that were exposed using the mask. In addition, average CD measurement was tried in order to improve the correlation. Photomask Technology 2009, edited by Larry S. Zurbrick, M. Warren Montgomery, Proc. of SPIE Vol. 7488, 748832 ·


23rd Annual BACUS Symposium on Photomask Technology | 2003

Improved Image Placement Performance of HL-7000M

Masaomi Tanaka; Hiroyuki Ito; Hiroyuki Takahashi; Kazuyoshi Oonuki; Yasuhiro Kadowaki; Hidetoshi Sato; Hajime Kawano; Zhigang Wang; Kazui Mizuno; Genya Matsuoka

HL-7000M electron beam (EB) lithography system has been developed as a leading edge mask writer for the generation of 90 nm node production and 65 nm node development. It is capable of handling large volume data files such as full Optical Proximity Correction (OPC) patterns and angled patterns for System on Chip (SoC). Aiming at the technological requirements of the International Technology Roadmap for Semiconductors (ITRS) 2002 Update, a newly designed electron optics column generating a vector-scan variable shaped beam and a digital disposition system with a storage area network technology have been implemented into HL-7000M. This new high-resolution column and other mechanical components have restrained the beam drift and fluctuation factors. The improved octapole electrostatic deflectors with new dynamic focus correction and gain alignment methods have been built into the object lens system of the column. These enhanced features are worth mentioning due to the achievement of HL-7000Ms Image Placement (IP) performance. Its accuracy in 3σ of a 14 x 14 global grid matching result over an area of 135 mm x 135 mm measured by Leica LMS IPRO are X: 6.09 nm and Y: 7.85 nm. In addition, the shot astigmatism correction has been in the development and testing process and is expected to improve the local image placement accuracy dramatically.


22nd Annual BACUS Symposium on Photomask Technology | 2002

Advanced CD Linearity Improvement for Multi-Project Wafers and SoC at 95 nm Technology Node

Jeremy Lu; Nicole L. Sandlin; Hidetoshi Sato; Colbert Lu; Nicole Cheng; Torey Huang; Clyde Su; Melisa J. Buie

The continuous shrinking of design rules results in tighter specifications for linearity in advanced mask processing. Specifically, the increasing need for multiple devices on a single reticle set, e.g., multiproject wafers (MPWs) and systems on a chip (SoC), drives development in this area. Advanced masks were prepared with positive and negative chemically amplified resist (CAR) written on the Hitachi HL-950M. Post-exposure bake was performed in a double-sided proximity baking system; development was done using a spray-puddle method. Etch experiments were performed in the Etec Systems Tetra photomask etch chamber. Linearity measurements were performed using the Hitachi S-7840 CD SEM and the Leica LWM 250 DUV. Both clear and dark isolated and dense features were measured. The current work examines the impact of various etch process parameters (Cl2/O2 ratio, gas flow, pressure, source power) on CD linearity between 400 nm and 1.25 μm. A full factorial-designed orthogonal experiment was performed to determine the main effects and any interactions that might impact the linearity performance. Pressure and total flow showed a strong influence on linearity.


Archive | 2008

Device allocation changing method

Tomoki Sekiguchi; Sachie Tajima; Hidetoshi Sato


Archive | 2008

METHOD OF MIGRATION BETWEEN VIRTUAL MACHINE AND PHYSICAL MACHINE AND MACHINE SYSTEM THEREOF

Tomoki Sekiguchi; Hidetoshi Sato; Taisei Yoshino


Archive | 2008

Method of checking a possibility of executing a virtual machine

Tomoki Sekiguchi; Hidetoshi Sato


Archive | 2009

Pattern measurement methods and pattern measurement equipment

Hidetoshi Sato; Ryoichi Matsuoka


Archive | 2010

Sample Transfer Unit and Sample Transferring Method

Takashi Gunji; Hidetoshi Sato; Katsuya Kawakami; Hideki Yatabe

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