Takumichi Sutani

A new matching engine between design layout and SEM image of semiconductor device

Optical proximity correction (OPC) plays a vital role in the lithography process development of current semiconductor devices. OPC is utilized to achieve the ideal pattern shape because of the limitations of optical resolution. However, the lithography process design has become increasingly more complex due to the abundant use of OPC features. Hence, metrology requests for CD-SEM have also become more complex and diverse in order to characterize the critical OPC models. The number of measurement points for OPC model evaluation has increased to several hundred points per layer, and metrology requests for realized pattern shapes on the wafer are no longer simple one-dimensional measurements. Metrology requests include not only the traditional line width measurements, but also edge placement error (EPE) and corner rounding to identify line end shortening. Several researchers have proposed using the design layout as a template instead of the SEM image for the recipe creation of CD-SEM and EPE measurement. However, it is very difficult to achieve good matching results between the design layout and the SEM image in practical processing times. Hitachi High-Technologies has developed a robust and quick matching engine between the design layout and SEM image bitmap. The new system, incorporating this new matching engine, can automatically create a practical recipe from the coordinate information of measurement point and the design layout information, such as GDSII. As a result, the new system can vastly reduce the amount of time and number of operations required to generate a several-hundred point CD-SEM recipe for OPC evaluation. This study demonstrates the capability and presents evaluation results of this new matching engine. This new capability has proven to be a viable solution for OPC evaluation, and its efficiency will allow for quicker information turns between design and manufacturing.

Concerning the influence of pattern symmetry on CD-SEM local overlay measurements for double patterning of complex shapes

We have developed a new local overlay measurement technique on actual device patterns using critical dimension scanning electron microscope (CD-SEM), which can be applied to 2D device structures such as an SRAM contact hole array or more complex shapes. CD-SEM overlay measurement can provide additional local overlay information at the site of device patterns, complementary to the conventional optical overlay data. The methodology includes the use of symmetrically arranged patterns to cancel out many process effects and reduce measurement uncertainty. The developed methodology was applied to local overlay measurement of double patterning contact hole layers of leading edge devices. Local overlay distribution was successfully captured on device structures on different length scale, and the result shows the possibility of assessing process induced shift on device structures and collecting denser sampling for better intra-chip overlay control. The measurement uncertainty of CD-SEM overlay metrology was assessed by comparing with conventional optical overlay metrology for 1D and 2D structures. Very good correlation was confirmed between SEM and optical overlay metrology with net residual error of ~1.1nm. Measurement variation associated with pattern roughness was analyzed for 1D structure, and identified as one of major variation sources for CD-SEM overlay metrology.

Enabling CD SEM metrology for 5nm technology node and beyond

The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated threedimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, IIIV, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.

Critical dimension scanning electron microscope local overlay measurement and its application for double patterning of complex shapes

We have developed a new local overlay measurement technique on actual device patterns using a critical dimension scanning electron microscope (CD-SEM), which can be applied to two-dimensional (2D) device structures such as a static random access memory contact hole array. CD-SEM overlay measurement can provide additional local overlay information at the site of device patterns, complementary to the optical overlay. The methodology includes the use of pattern symmetry to cancel out many process effects and reduce measurement uncertainty. CD-SEM overlay metrology was compared with conventional optical overlay metrology in terms of measurement uncertainty and overlay model analysis, and very good correlation was confirmed. The developed methodology was applied to local overlay measurement of double patterning contact hole layers of leading edge devices. The local overlay distribution was obtained across the device area, and spatial correlation of the overlay error vectors was examined over a large range of distances. The applications of CD-SEM overlay metrology were explored, and methodologies were introduced to examine both the overlay of double patterning contacts at the edge of an array and lithographic process-induced overlay shift of contacts. Finally, a hybrid optical CD-SEM overlay metrology was introduced in order to capture a high order, device weighted overlay response.

Spatial signature in local overlay measurements: what CD-SEM can tell us and optical measurements can not

This work explores the applications of CD-SEM overlay metrology for double patterned one-dimensional (1D) pitch split features as well as double patterned ensembles of two-dimensional (2D) complex shapes. Overlay model analysis of both optical overlay and CD-SEM is compared and found to give nearly equivalent results. Spatial correlation of the overlay vectors is examined over a large range of spatial distances. The smallest spatial distances are shown to have the highest degree of correlation. Correlation studies of local overlay in a globally uniform environment, suggest that the smallest sampling of overlay vectors need to be ~10-15μm, within the spatial sampling of this experiment. The smallest spatial distances are also found to have to tightest mean distributions. The distribution width of the CD-SEM overlay is found to scale linearly with log of the spatial distances over 4-5 orders of magnitude of spatial length. Methodologies are introduced to examine both the overlay of double pattern contacts at the edge of an array and lithographic process-induced overlay shift of contacts. Finally, a hybrid optical- CD-SEM overlay metrology is introduced in order to capture a high order, device weighted overlay response.

Evaluation of Hitachi CAD to CD-SEM metrology package for OPC model tuning and product devices OPC verification

Optical proximity corrections are widely used in semiconductor industry to compensate non-linear effects occurring when printing features smaller than exposure wavelength. Most advanced OPC software packages simulate optical behavior starting from a physical description of illumination and projection optics, while the characterization of resist development and etch loading effects is still performed empirically, with different approaches that, generally, require the collection of a huge amount of experimental data. Due to the wide variety of target patterns, which makes conventional CD-SEM recipe creation impossible, critical dimension (CD) measurements are usually performed manually, requiring long time and, despite the attention paid while measuring, with poor guarantee of repeatability. The introduction of 193nm resists, much more sensitive to SEM e-beam exposure if compared to 248nm materials, required increased attention to be paid on both focusing and measuring phases in order to obtain reliable results. As well as OPC model tuning, the verification of correction effectiveness on product devices is performed almost in the same way leading to the same kind of issues. In order to overcome most of these problems ST is evaluating a new CD metrology package from Hitachi High Technologies; this tool allows fully automatic CD measurements starting from GDS II coordinate input. The exact recognition of measurement locations is obtained through an algorithm, based on the superposition of the drawn GDS II layout to the SEM wafer images, which allows achieving high positioning accuracy. The introduction of the tool significantly reduces measuring time down to the range of normal automated CD measurement times, while guarantying improved repeatability and optimized conditions even with 193nm resists due to the possibility of defining different structures for addressing and focusing before the measurement. This new system opens new perspectives in OPC modeling giving the opportunity of a more accurate model tuning, required by 65 nm technology node, and enables an extensive product devices OPC verification presently impossible due to time and procedure issues.

The need for LWR metrology standardization: the imec roughness protocol

As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: Line Width Roughness (LWR) specifications are expected to be less than 2nm in the near term, and to drop below 1nm in just a few years. This is a daunting challenge and engineers throughout the industry are trying to meet these targets using every means at their disposal. However, although current efforts are surely admirable, we believe they are not enough. The fact is that a specification has a meaning only if there is an agreed methodology to verify if the criterion is met or not. Such a standardization is critical in any field of science and technology and the question that we need to ask ourselves today is whether we have a standardized LWR metrology or not. In other words, if a single reference sample were provided, would everyone measuring it get reasonably comparable results? We came to realize that this is not the case and that the observed spread in the results throughout the industry is quite large. In our opinion, this makes the comparison of LWR data among institutions, or to a specification, very difficult. In this paper, we report the spread of measured LWR data across the semiconductor industry. We investigate the impact of image acquisition, measurement algorithm, and frequency analysis parameters on LWR metrology. We review critically some of the International Technology Roadmap for Semiconductors (ITRS) metrology guidelines (such as measurement box length larger than 2μm and the need to correct for SEM noise). We compare the SEM roughness results to AFM measurements. Finally, we propose a standardized LWR measurement protocol - the imec Roughness Protocol (iRP) - intended to ensure that every time LWR measurements are compared (from various sources or to specifications), the comparison is sensible and sound. We deeply believe that the industry is at a point where it is imperative to guarantee that when talking about a critical parameter such like LWR, everyone speaks the same language, which is not currently the case.

Advanced CD-SEM solution for edge placement error characterization of BEOL pitch 32nm metal layers

Metrology plays an important role in edge placement error (EPE) budgeting. Control for multi-patterning applications as new critical distances needs to be measured (edge to edge) and requirements become tighter and tighter in terms of accuracy and precision. In this paper we focus on imec iN7 BEOL platform and particularly on M2 patterning scheme using SAQP + block EUV for a 7.5 track logic design. Being able to characterize block to SAQP edge misplacement is important in a budgeting exercise (1) but is also extremely difficult due to challenging edge detection with CD-SEM (similar materials, thin layers, short distances, 3D features). In this study we develop an advanced solution to measure block to SAQP placement, we characterize it in terms of sensitivity, precision and accuracy through the comparison to reference metrology. In a second phase, the methodology is applied to budget local effects and the results are compared to the characterization of the SAQP and block independently.