Hideyuki Aota

CMOS voltage reference based on gate work function differences in poly-Si controlled by conductivity type and impurity concentration

A new CMOS voltage reference circuit consisting of two pairs of transistors is presented. One pair exhibits a threshold voltage difference with a negative temperature coefficient (-0.49 mV//spl deg/C), while the other exhibits a positive temperature coefficient (+0.17 mV//spl deg/C). The circuit was robust to process variations and exhibited excellent temperature independence and stable output voltage. Aside from conductivity type and impurity concentrations of gate electrodes, transistors in the pairs were identical, meaning that the system was robust with respect to process fluctuations. Measurements of the voltage reference circuit without trimming adjustments revealed that it had excellent output voltage reproducibility of within /spl plusmn/2%, low temperature coefficient of less than 80 ppm//spl deg/C, and low current consumption of 0.6 /spl mu/A.

Evaluation of Packaging-Induced Performance Change for Small-Scale Analog IC

The impact of packaging-induced circuit performance changes for a small-scale integrated circuit (IC) smaller than 1.0 mm 2 has been evaluated by a new method with specially designed test chips. Analog circuits such as power management ICs for portable electronic devices are small-scale chips and require high-accuracy operation. Multiple test chips with different resistor locations have been fabricated and measured by die-to-die correspondence, after which one distribution chart was reproduced from all of the measurement results. The present method enables the characteristic distribution on the chip surface to visualize not only the electrical parametric distribution but also the residual stress distribution, even though small-scale ICs have a limited number of bonding pads. In addition, a new method for evaluating the circuit performance change of an analog circuit due to stress-induced parametric changes is presented.

Prediction of stress-induced characteristic changes for small-scale analog IC

Stress-induced parametric changes during the resin-molded packaging of a small-scale integrated circuit (IC) smaller than 1.0 mm2 have been evaluated by a specially designed test chip. Multiple test chips with different resistor locations have been fabricated and measured by die-to-die correspondence. One contour plot was reproduced from the measurement results. The present paper shows the distribution of parametric change for the small-scale IC. In addition, a new method for evaluating the circuit performance change due to stress-induced parametric changes is presented.