Hirobumi Watanabe

CMOS voltage reference based on gate work function differences in poly-Si controlled by conductivity type and impurity concentration

A new CMOS voltage reference circuit consisting of two pairs of transistors is presented. One pair exhibits a threshold voltage difference with a negative temperature coefficient (-0.49 mV//spl deg/C), while the other exhibits a positive temperature coefficient (+0.17 mV//spl deg/C). The circuit was robust to process variations and exhibited excellent temperature independence and stable output voltage. Aside from conductivity type and impurity concentrations of gate electrodes, transistors in the pairs were identical, meaning that the system was robust with respect to process fluctuations. Measurements of the voltage reference circuit without trimming adjustments revealed that it had excellent output voltage reproducibility of within /spl plusmn/2%, low temperature coefficient of less than 80 ppm//spl deg/C, and low current consumption of 0.6 /spl mu/A.

Operation of a Work Function Type SOI Temperature Sensor up to 250°C

Bulk-Si ICs cannot operate over 150degC, due to the reverse bias leakage current of the p-n junction in MOSFETs or diode components. In this paper, we investigated a work function type temperature sensor on a SOI substrate, which generates voltage output by the work function difference and is superior to diode-type temperature sensors at high temperature. This SOI temperature sensor is operated up to 250degC, and the consumption current is one order of magnitude lower than that of a bulk-Si temperature sensor.

Evaluation of Packaging-Induced Performance Change for Small-Scale Analog IC

The impact of packaging-induced circuit performance changes for a small-scale integrated circuit (IC) smaller than 1.0 mm 2 has been evaluated by a new method with specially designed test chips. Analog circuits such as power management ICs for portable electronic devices are small-scale chips and require high-accuracy operation. Multiple test chips with different resistor locations have been fabricated and measured by die-to-die correspondence, after which one distribution chart was reproduced from all of the measurement results. The present method enables the characteristic distribution on the chip surface to visualize not only the electrical parametric distribution but also the residual stress distribution, even though small-scale ICs have a limited number of bonding pads. In addition, a new method for evaluating the circuit performance change of an analog circuit due to stress-induced parametric changes is presented.

Low power and more accurate temperature sensor with an integrated dual slope AD converter

A digital temperature sensor with an integrated dual slope ADC is recently proposed. In the present study, a smaller digital temperature sensor is realized by integrating a dual-slope capacitor, which is usually attached to an integrated circuit device. A proper designed circuit can supply a voltage of 2.3 V and a consumption current of 50 μA. Adopting the CV characteristics of the MOS capacitor allows the sensing accuracy to be improved by 0.5°C.

Image sensor with new trench-gated phototransistor

Here we present an image sensor with a new type of phototransistor that realizes a wide dynamic range for photons. The proposed phototransistor has a new function of dynamic range compression, so that the output signal is not limited by the power supply voltage.

Evaluation of dynamic bonding stress and interlayer cracking using a combo sensor

Crack defect in the interlayers of semiconductor chips due to assembly stress can be a serious problem. To analyze the crack-generating stress, we fabricated a combo sensor that enables simultaneous evaluation of stress and cracking under the bonding pad. Dynamic analysis of the bonding process with this sensor in situ showed that the cracks are generated by stress concentration in alloy aggregates that form during the initial stage of ultrasonic bonding.

Prediction of stress-induced characteristic changes for small-scale analog IC

Stress-induced parametric changes during the resin-molded packaging of a small-scale integrated circuit (IC) smaller than 1.0 mm2 have been evaluated by a specially designed test chip. Multiple test chips with different resistor locations have been fabricated and measured by die-to-die correspondence. One contour plot was reproduced from the measurement results. The present paper shows the distribution of parametric change for the small-scale IC. In addition, a new method for evaluating the circuit performance change due to stress-induced parametric changes is presented.

Grain Boundary Properties of Boron-Doped Polycrystalline Si1-XGeX Resistors with Small Process Fluctuation and Small Drift for High Precision Analog ICs

The resistivity of poly-Si1-XGeX (X=0.0, 0.2, 0.4) films was studied in terms of process fluctuation and long-term stability. Experimental results demonstrated that poly-Si0.6Ge0.4 is superior to poly-Si because of its low process fluctuation of less than 3% across a wafer and significant reduction of resistivity-drift. The measured Hall mobility and trapping density reveal that the atomic configuration at the grain boundary of boron-doped poly-Si1-XGeX film differs from that of the conventional poly-Si film. Under hydrogen exposure, the electrical properties of poly-Si1-XGeX films in a wide range of carrier concentration are more stable than those of poly-Si, because of a smaller amount of dangling bonds, stronger bonding energy to hydrogen and more segregation of boron atoms at poly-Si1-XGeX boundaries. These results indicate that the poly-Si1-XGeX resistors are superior to poly-Si ones for obtaining high precision and low power analog circuits.