Hideyuki Fukushi

Wafer-level hermetic packaging technology for MEMS using anodically-bondable LTCC wafer

This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature cofired ceramic (LTCC) wafer, in which electrical feedthroughs and passive components can be embedded. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of heat shock (−40 °C/+150 °C, 30 min/30 min) by diaphragm method. The width of seal rings necessary for hermetic sealing of saw-diced chips is 0.1 mm or less. Electrical connection between MEMS on a Si wafer and feedthroughs in the LTCC wafer was established using Sn-containing metal stack simultaneously with anodic bonding. The developed wafer-level hermetic packaging technology is ready for practical applications.

An SOI tactile sensor with a quad seesaw electrode for 3-axis complete differential detection

This paper presents a novel SOI capacitive tactile sensor with a quad-seesaw electrode for 3-axis complete differential detection, which enables integration with a CMOS. For differentially detecting 3-axis forces, the tactile sensor is composed of four rotating plates individually suspended by torsion beams. In this study, to demonstrate the working principle, we fabricated a test device that integrates an SOI substrate with the quad-seesaw electrode and an anodically bondable LTCC substrate with fixed electrodes as an alternative to the CMOS. The experimental results of the test device successfully demonstrated the working principle as well as 3-axis differential detection with a matrix operation.

Versatile wafer-level hermetic packaging technology using anodically-bondable LTCC wafer with compliant porous gold bumps spontaneously formed in wet-etched cavities

This paper reports simple and versatile technology for hermetically capping MEMS with a wet-etched LTCC (low temperature cofired ceramic) wafer by standard anodic bonding process, in which the MEMS and Au vias in the LTCC wafer are electrically connected by porous Au bumps. The porous Au bump is spontaneously formed from a part of the Au via by wet-etching the LTCC wafer, because glass-based filler in the Au via is etched away and leaves pores. Excellent compliance of the porous Au bump absorbs error in the height of the electrodes etc. The wet-etched LTCC wafer was anodically bonded with an SOI wafer with diaphragms and Au electrodes under a standard condition. 100% yield of both hermetic sealing and electrical connection was confirmed. A thermal shock test was performed, and no significant change of sealing pressure and the resistance of electrical connections was observed at least up to 3000 cycles.

Low-temperature aluminum thermo-compression wafer bonding with tin antioxidation layer for hermetic sealing of MEMS

Hermetic Al-Al thermo-compression bonding was demonstrated at the lowest temperature ever reported, 370-390°C, using a thin antioxidation capping layer of Sn. A key factor of hermetic sealing is bonding pressure enough to compress the bonding interlayer metal. From the same point of view, a narrower sealing frame for stress concentration, thicker Al and a higher bonding temperature within the allowable range (<;400°C) are favorable for high yield hermetic sealing. Judging from Al-Sn phase diagram, Sn should uniformly and sparsely exist among Al grains as Al-Sn eutectic, which was also supported by the cross-sectional observation of the bonding interlayer. In such a microstructure, Al-Al direct metal bonding, which is stable at Pb-free solder reflow temperature, should be created. Al is the standard metal of CMOS backend, free from the risk of metal contamination and inexpensive, and thus the bonding technology described in this paper is useful for MEMS-CMOS integration.

Electrical connection using submicron porous gold bumps for wafer-level packaging of mems using anodically-bondable LTCC wafer

An anodically-bondable low temperature cofired ceramic (LTCC) wafer offers a versatile, clean and reliable wafer-level hermetic packaging for MEMS. This paper reports electrical connection in parallel with anodic bonding between MEMS on a Si wafer and vias in the LTCC wafer using porous Au bump. The Au bump is made of submicron Au particles, and so compliant as it easily absorbs large height difference. The LTCC wafer with the Au bumps and an SOI wafer with Au/Pt/Cr pads and diaphragms were anodically bonded. 100 % yield of both electrical connection and hermetic sealing was demonstrated. Heat cycle test confirmed the reliability of both electrical connection and hermeticity. In addition, the transfer of the porous Au bumps from a mother glass wafer to a target LTCC wafer was demonstrated. This method dispenses with the fabrication of the porous Au bumps by users, which includes non-standard processes.

Comprehensive study on wafer-level vacuum packaging using anodically-bondable LTCC wafer and thin film getter

An anodically-bondable low-temperature cofired ceramic (LTCC) wafer is a new wafer-level packaging material for micro electro mechanical systems (MEMS). It provides 3-dimensional metal interconnection inside, and enables hermetic sealing, which was guaranteed by automobile-grade thermal cycling tests. In this study, the sealing pressure was first investigated under various anodic bonding conditions with and without two types of thin film getter (PaGe getter, Saes Getters or Ti getter). The vacuum sealing pressure was a few kPa or even higher, and more importantly, often different for each sample without the thin film getter. On the other hand, samples with the getter always exhibited good vacuum level, which was below the detection limit (80 Pa) of zero-balance method using a Si diaphragm. Typical process conditions for borosilicate glass on commercially-available bonding tools work well.

Comprehensive Die Shear Test of Silicon Packages Bonded by Thermocompression of Al Layers with Thin Sn Capping or Insertions

Thermocompression bonding for wafer-level hermetic packaging was demonstrated at the lowest temperature of 370 to 390 °C ever reported using Al films with thin Sn capping or insertions as bonding layer. For shrinking the chip size of MEMS (micro electro mechanical systems), a smaller size of wafer-level packaging and MEMS–ASIC (application specific integrated circuit) integration are of great importance. Metal-based bonding under the temperature of CMOS (complementary metal-oxide-semiconductor) backend process is a key technology, and Al is one of the best candidates for bonding metal in terms of CMOS compatibility. In this study, after the thermocompression bonding of two substrates, the shear fracture strength of dies was measured by a bonding tester, and the shear-fractured surfaces were observed by SEM (scanning electron microscope), EDX (energy dispersive X-ray spectrometry), and a surface profiler to clarify where the shear fracture took place. We confirmed two kinds of fracture mode. One mode is Si bulk fracture mode, where the die shear strength is 41.6 to 209 MPa, proportionally depending on the area of Si fracture. The other mode is bonding interface fracture mode, where the die shear strength is 32.8 to 97.4 MPa. Regardless of the fracture modes, the minimum die shear strength is practical for wafer-level MEMS packaging.

Low temperature hermetic sealing by aluminum thermocompression bonding using tin intermediate layer

Aluminum with Sn intermediate layer shows very large deformation even below 400°C. Using this new layer structure as sealing metal, high yield hermetic package of MEMS was demonstrated at only 370°C without any treatment of surface oxide removal. During bonding, the bonding metal is significantly pressed (the reduction rate of thickness ∼90%), which guarantees hermeticity at high yield. Based on SEM, EDX and TEM analysis, the role of tin for hermetic sealing and the mechanism of softening of this layer structure were discussed.

Low-stress dicing assisted by pulsed laser for multilayer MEMS

We have developed a novel debris-free in-air laser dicing technology, which is expected to give less failure of MEMS devices and hence improves yields. Our technology combines two processes: a dicing guide fabrication and a wafer separation process. The first process is internal transformation using a nanosecond Nd:YVO4 laser with high repetition rate and/or a pulsed fiber laser with 200ns pulsewidth. The laser pulses are focused inside the MEMS wafer without surface ablation. In order to make cross-sectional internal transformation, the laser beam is scanned several times with defocusing. The laser scanning speed per each scanning is 100-700 mm/sec depending on the layer material, the machining time is much faster than the conventional blade dicing. The second process is non-contact separation by thermally-induced crack propagation using a CO2 laser or mechanical separation by bending stress. In the each separation process, the internal transformation fabricated in the first process worked well as the guide of separation, and the processed wafer was diced with low stress. This dicing technology was applied for 4-inch MEMS wafers, e.g. pressure sensors, etc., and the sensor chips were separated without mechanical damages.

Debris-free low-stress laser dicing for multi-layered MEMS wafers

We have developed a novel debris-free low-stress laser dicing technology for multi-layered MEMS wafers, which are generally consisted of glass and Si. Our technology combines two processes: dicing guide fabrication and wafer separation process. The first process is the internal transformation using a pulsed 1µm laser. The second process is non-contact separation by thermally-induced crack propagation using a CO2 laser or mechanical separation by bending stress. We tested several pulsed lasers with different pulsewidths, including a Nd:YVO4 laser and an Yb fiber laser for generating the internal transformation in silicon and/or glass. The internal transformed lines worked well as a guide of the separation. We found that the internal transformation only in Si layer was enough for dicing the glass/Si double-layered wafer. Also the thermal stress induced by the CO2 laser was quite effective to propagate the crack inside the glass layer without internal transformation. The double-layered wafer consisting of glass and silicon can be diced in low stress by our technology.We have developed a novel debris-free low-stress laser dicing technology for multi-layered MEMS wafers, which are generally consisted of glass and Si. Our technology combines two processes: dicing guide fabrication and wafer separation process. The first process is the internal transformation using a pulsed 1µm laser. The second process is non-contact separation by thermally-induced crack propagation using a CO2 laser or mechanical separation by bending stress. We tested several pulsed lasers with different pulsewidths, including a Nd:YVO4 laser and an Yb fiber laser for generating the internal transformation in silicon and/or glass. The internal transformed lines worked well as a guide of the separation. We found that the internal transformation only in Si layer was enough for dicing the glass/Si double-layered wafer. Also the thermal stress induced by the CO2 laser was quite effective to propagate the crack inside the glass layer without internal transformation. The double-layered wafer consisting of gl...