Hikari Murai

New halogen‐free materials for PWB, HDI and advanced package substrate

Recently, the requirement of the printed wiring boards (PWBs) of environmental harmony type has risen rapidly. We have developed the core technologies of halogen‐free. They consist of resin system technology and high filler content technology. The point of the resin technology is the development of a new resin system (RO resin) which takes nitrogen into the molecule frame in a large quantity. The point of the high filler content technology is the development of a new filler interphase control system (FICS) which enables the high dispersion of fillers. A variety of halogen‐free substrates which can be applied to the diversified needs have been developed by combining these technologies. They are MCL‐RO‐67G, thin laminate for the multi‐layer PWBs, MCF‐4000G, build‐up material for high density interconnect (HDI) , and MCL‐E‐679F(G), high Tg laminate for the advanced plastic IC packages (PKGs) and PWBs. These materials have excellent heat‐resistance, and are suitable for lead‐free solder as well. The robustnes...

New fine line fabrication technology on glass-cloth prepreg without insulating films for PKG substrate

As electronic parts increase its performance and miniaturize in its size, package substrates are demanded to be thinner and higher in density. But higher density substrates using insulating films give higher warpage values when they are very thin, due to its low modulus. Packages with glass-cloth prepreg as its outer-layer have lower warpage, but making a 40 μm pitch package with them are difficult because it cannot adapt to the semi-additive method. Conventional insulating films can be applied to the semi-additive method; however, a process of roughing the surface of the insulating films by chemicals is required, causing the limitation of material of insulating films. Therefore, we developed a new technology of semi-additive primer (SAPP) with glass-cloth prepregs which allows higher density and lower warpage for substrates. Under 30 μm pitch wiring of SAPP applied substrates were easier compared to conventional substrates made from the insulating film semi-additive method. Also, the roughening process (Ra=0.50–0.60 μm) of conventional insulating films to achieve adhesion strength with plated copper makes high density wiring difficult. But the new SAPP system has a surface roughness of Ra <0.25 μm with high adhesive strength which allows easy high density wiring. It has been made clear that by providing a new adhesive-agent layer, peel strength equivalent to that of the roughened insulating film (0.7 kN/m or more) can be obtained with sufficient reliability. The thinner package boards consisting of our new low-CTE and high modulus insulation prepreg E-700G(R) and SAPP have lower warpage than that of build-up structure and coreless structure using conventional insulating films. The package substrates made of SAPP with E-700G(R) core show low coefficient of thermal expansion (9–10 ppm/°C) and high modulus of tensile elasticity (32 GPa), with 20 μm pitch wiring possible.

Newly developed ultra low CTE materials for thin core PKG

To achieve the recent improvements in miniaturization and performance of mobile devices (Smart phone, Tablet PC etc.), the semiconductor PKG substrate installed in these devices is demanded to be thinner and higher in density. However, the thinner PKG substrate may cause poor connection reliability due to increased warpage by soldering. The ultra low CTE (Coefficient of thermal expansion) core material has been required as the key solution for the reduction of the warpage of the thinner PKG substrate such as PoP (Package on package). We have just developed two types of ultra low CTE core materials named E-705G and E-800G to meet with the requirement, applying our original resin systems and the filler surface treatment technologies. The developed materials show the ultra low CTE(X, Y) property (2.8-3.3 ppm/°C) similar to that of glass fabric itself. Also E-705G has high flexural modulus over 33-36 GPa at room temperature. Regarding E-800G, it has the good dielectric characteristics (lower dielectric constant and dissipation factor), can be applicable higher speed PKG. Both of the materials have high reliability and high heat resistance which is suitable for the lead-free soldering process. Confirming the warpage property, we evaluated the warpage behavior of PoP (bottom) constructions before/after assembly process. The newly developed materials showed the much lower warpage than the conventional low CTE material.

Ultra low CTE (1.8 ppm/°C) core material for next generation thin CSP

Along with the advancement in miniaturizing of mobile devices, typified by smart phones and tablet PCs, the semiconductor PKG substrate installed in these devices is demanded to be thinner and higher in density. As one of the most innovative solutions, the PoP (package on package) technology, which has the three-dimensional construction, has been expanding rapidly in recent years. However, the thinner PKG such as PoP tends to warp at the assembly process and cause the decrease in the connection reliability. Therefore ultra low CTE (coefficient of thermal expansion) core materials have been needed as a key solution for the reduction of the warpage for PoP. Recently, we have developed new ultra low CTE core material named E-770G for next generation thin CSP, applying new resin systems, featuring low shrinkage and low residual stress. In particular, E-770G has achieved ultra low CTE of 1.8 ppm/°C which leads to significant reduction of the warpage. Furthermore, it has low dissipation factor at high frequencies (Df: 0.005 at 1 GHz). So its also applicable to high speed PKG applications. Confirming the warpage property, we evaluated the warpage behavior of the bottom PKG before/after assembly process. E-770G showed the much lower warpage than the conventional ultra low CTE core material.

Airfoil: A new fine line fabrication technology on glass-cloth prepreg without insulating films for PKG substrate

As electronic parts increase its performance and miniaturize the size, package substrates are demanded to be thinner as well as higher in density. Thin packages such as Chip Scale Package (CSP) require high elastic modulus and low coefficient of thermal expansion with high density wiring to reduce warpage. To enable high density wiring, while maintaining crucial properties and minimal warpage, various fine line fabrications applied to glass-cloth prepreg have been investigated. The wiring processes with glass-cloth prepreg have made much progress from the subtractive method to SAP (Semi-Additive Process with primer for glass-cloth prepreg) and MSAP (modified SAP with ultra-thin copper). These have been achieved by decreasing the thickness of the to-be-etched copper layer. In the conventional SAP, the roughened surface of the primer is formed by imprinting the low profile copper (Ra = 0.3-0.5 μm) instead of the chemical etching of insulation film [1]. However, the flatness of the surface of Ra;0.3-0.5 μm makes the wiring under 30 μm pitch difficult. Therefore, we developed the new primer “Airfoil”, that can provide the excellent adhesive property with plated copper via chemical interaction. Airfoil has functional groups interacting with plated copper which provide the excellent peel strength despite of smooth surface (Ra<;0.1 μm). In addition, the high peel strength of Airfoil can be maintained for various types of prepregs by the diffusion controlled adhesive process. By applying Airfoil with glass-cloth prepreg, the wiring of 10 μm pitch was successfully fabricated by the SAP. Since Airfoil is very thin, it does not influence the prime properties of glass-cloth prepreg (e.g. elastic modulus, coefficient of thermal expansion, dielectric properties). Consequently, the package substrates of Airfoil with prepreg show the low coefficient of thermal expansion and high elastic modulus with 10 μm pitch wiring.

New ultra low CTE material to reduce the warpage of thinner PKG

Along with the advancement in miniaturizing of mobile devices, typified by smart phones and tablet PCs, the semiconductor PKG substrate installed in these devices is demanded to be thinner and higher in density. As one of the most innovative solutions, the PoP (package on package) technology, which has the three-dimensional construction, has been expanding rapidly in recent years. However, the thinner PKG substrate tends to warp at the assembly process and cause the decrease in the connection reliability. Therefore ultra low CTE (coefficient of thermal expansion) materials have been needed as a key solution for the reduction of the warpage for thinner PKG substrates. Recently, we have developed new ultra low CTE material named E-770G for next-generation semiconductor PKG substrate, applying new resin systems, featuring low shrinkage and low residual stress. In particular, E-770G has achieved ultra low CTE (X) of 1.8 ppm/°C which leads to significant reduction of the warpage. Furthermore, it has low dissipation factor at high frequencies (Df: 0.005 at 1 GHz). So its also applicable to high speed PKG applications. Confirming the warpage property, we evaluated the warpage behavior of thinner PKG substrate before/after assembly process. E-770G showed the much lower warpage than the conventional ultra low CTE material.

Newly developed ultralow CTE materials for thinner PKG applications

The higher density packaging technologies have been required to reduce the area of substrate for smaller portable handheld products and devices such as smart phones and tablet PCs. So, the three-dimensional packaging is becoming to be a key technology to minimize the total size of products and devices. However, the thinner construction of PoP (package on package) may cause the poor connection reliability because of the warpage of the substrate at the soldering process. So, the reduction of the warpage of the substrate by the ultralow CTE (coefficient of thermal expansion) materials may be the key to overcome. Recently, we have developed two types of ultralow CTE materials to meet with the requirement applying our new resin systems and a filler treatment technology. The developed materials show the ultralow CTE(X) of 2.8-3.3 ppm/OC which is close to that of the glass fabric. The resulted warpage using the material is much lower than that of the conventional low CTE material. We are also developing a technology for the further lowering of CTE for future applications.

Halogen-free materials for PWB and advanced package substrate

We have developed halogen-free technologies, consisting of resin systems with high filler content. The point of the technology is the development of a new resin system (RO resin) which incorporates nitrogen into the molecule frame in large quantities. The high filler content technology develops a new filler interphase control system (FICS) which enables the high dispersion of fillers. A variety of halogen-free substrates which can be applied to diversified needs have been developed by combining these technologies. They are MCL-RO-67G, a thin laminate for the multi-layer PWBs, MCF-4000G, a build-up material for high density interconnect (HDI), and MCL-E-679F(G), a high Tg laminate for advanced plastic IC packages (PKGs) and PWBs. These materials have excellent heat-resistance, and are suitable for lead-free solder. The robustness towards temperature, humidity and frequency of those materials is better than that of current materials. The synthetic board design of environmental harmony type becomes easy by combined use of these materials.