Himanshu Khatri

Distortion in Current Commutating Passive CMOS Downconversion Mixers

CMOS passive mixer linearity is analyzed using a Volterra-series analysis and closed-form expressions for IIP2, two-tone IIP3, and cross-modulation IIP3 are presented, exhibiting dependence upon the mixer source and load impedances. Design guidelines are suggested for improving the mixer linearity performance. Accurate expressions are presented for the input impedance of an ideal passive mixer with an arbitrary load impedance. The calculations are in close agreement with the measured results and the simulated response.

Integrated RF Interference Suppression Filter Design Using Bond-Wire Inductors

Design techniques are presented for the realization of high-performance integrated interference suppression filters using bond-wire inductors. A new configuration is proposed for mitigating the impact of mutual coupling between the bond wires. A differential low-noise amplifier with an integrated on-chip passive interference suppression filter is designed at 2.1 GHz in a 0.18-mum CMOS process, and achieves a transmit leakage suppression of 10 dB at 190-MHz offset. The differential filter uses metal-insulator-metal capacitors and bond-wire inductors and occupies only 0.22 mm2. The cascaded system achieves a measured gain of 9.5 dB with a 1.6-dB noise figure and -5 dBm out-of-band IIP3 and consumes 11 mA from a 2-V supply.

An Active Transmitter Leakage Suppression Technique for CMOS SAW-Less CDMA Receivers

A CDMA-2000 receiver without interstage RF SAW filter is presented. An active bandpass sink filter is proposed to selectively filter the transmitted leakage after the downconversion mixer. The impact on receiver noise and linearity performances is discussed. This technique improves the triple-beat (TB) and IIP2 of the receivers by 6.5 dB each, at the expense of a small increase in DC current and noise. Designed in 0.18 μm CMOS technology, the receiver achieves 45 dB gain with uncalibrated IIP2 of +46 dBm and triple-beat of 69 dB.

A SAW-less CDMA receiver front-end with single-ended LNA and single-balanced mixer with 25% duty-cycle LO in 65nm CMOS

A fully integrated SAW-less direct conversion CDMA receiver with single-ended LNA and modified single-balanced passive mixer is manufactured in a 65 nm digital CMOS process. The measured receiver gain at 1.96 GHz was 37 dB, NF was 3 dB, IIP2 was +62 dBm, and cross-modulation triple beat (TB) was 65 dB.

A SAW-less CMOS CDMA receiver with active Tx filtering

A CDMA-2000 receiver that eliminates the interstage SAW filter is presented. An active technique is proposed for filtering the transmitter leakage after downconversion. This technique improves the triple-beat (TB) and IIP2 performances by 6.5 dB each, at the expense of a small increase in DC current and noise.

On-chip monolithic filters for receiver interference suppression using bond-wire inductors

Two passive LC filters are fabricated in a 0.18 mum BiCMOS process for interference suppression in WCDMA applications. A single-pole filter achieves an insertion loss of 1dB at 2.14GHz and suppression of 12dB at 1.95GHz, while the three-pole filter has insertion loss of 8dB at 2.3GHz and provides a suppression of 23dB at 2.1GHz. Both filters are implemented using MIM capacitors and bond wire inductors

Simulation of intermodulation distortion in passive CMOS FET mixers

The simulation of third-order intermodulation distortion in a passive CMOS FET mixer will typically predict a fictitious 2:1 slope using the industry standard EKV, BSIM3 and BSIM4 models. This phenomenon has been attributed to the discontinuity in the second-order derivatives of the drain-current and the terminal charge model. This paper establishes the connection between the discontinuous derivatives and the resulting intermodulation distortion slope and provides experimental verification.