Prasad S. Gudem

A high average-efficiency SiGe HBT power amplifier for WCDMA handset applications

The linearity of a silicon-germanium (SiGe) HBT power amplifier (PA) is analyzed with the help of a power-dependent coefficient Volterra technique. The effect of emitter inductance is included and the dominant sources of nonlinearity are identified. A dynamic current biasing technique is developed to improve the average power efficiency for wide-band code-division multiple-access (WCDMA) PAs. The average power efficiency is improved by more than a factor of two compared to a typical class-AB operation, while the power gain keeps roughly constant. The measured adjacent channel power ratio with 5and 10-MHz offsets at 23.9-dBm average channel output power are -33 and -58.8 dBc, respectively, and satisfies the Third-generation partnership project WCDMA specifications. The output power at the 1-dB compression point is 25.9 dBm

Distortion in Current Commutating Passive CMOS Downconversion Mixers

CMOS passive mixer linearity is analyzed using a Volterra-series analysis and closed-form expressions for IIP2, two-tone IIP3, and cross-modulation IIP3 are presented, exhibiting dependence upon the mixer source and load impedances. Design guidelines are suggested for improving the mixer linearity performance. Accurate expressions are presented for the input impedance of an ideal passive mixer with an arbitrary load impedance. The calculations are in close agreement with the measured results and the simulated response.

Hybrid Transformer-Based Tunable Differential Duplexer in a 90-nm CMOS Process

Practical implementation of monolithic hybrid transformer duplexers have been limited by the poor common-mode isolation. In this paper, a differential hybrid transformer duplexer that covers 3GPP bands I, II, III, and IX between 1.7 and 2.2 GHz is introduced. It achieves a differential to differential isolation of 60 dB in the transmit (TX) band and 40 dB in the receive (RX) band, and a differential to common-mode isolation of 60 dB in both bands. The duplexer with a cascaded low-noise amplifier (LNA) achieves a noise figure of 5.6 dB in the RX path and an insertion loss of 3.7 dB in the TX path. The duplexer and LNA are implemented in a 90-nm CMOS process, consume 20 mA, and occupy an active area of 0.6 mm2.

Analysis of envelope signal injection for improvement of RF amplifier intermodulation distortion

Adaptive bias techniques based on envelope signal power detection have been proposed for linearity enhancement and dc current reduction in RF amplifiers. Experimental results show an improvement in amplifier linearity, although asymmetric intermodulation distortion (IMD) was observed. This work rigorously studies the effects of the envelope signal injection on amplifier distortion using the Volterra series formulations. The results intuitively explain the spectral regrowth asymmetry, and point to a design technique in which third-order IMD can be optimally cancelled. The theory was verified through comparison to measurement and simulation results.

Digital-IF WCDMA handset transmitter IC in 0.25 /spl mu/m SiGe BiCMOS

Implemented in a 0.25-/spl mu/m SiGe BiCMOS process, a highly integrated low-power transmitter IC (TxIC) is developed for wideband code-division multiple-access handset applications. Based on a digital-IF heterodyne architecture, it eliminates the external IF surface acoustic wave filter by adopting a meticulous frequency plan and a special-purpose second-order-hold D/A conversion scheme. The TxIC features a low-power high-speed D/A converter designed to drive a dominantly capacitive load. For the upconversion mixer and the RF amplifier, adaptive biases are designed to minimize the quiescent power consumption and to provide current boost only when needed. The TxIC achieves <1% EVM. It consumes 180 mW (3-V supply) for the maximum output power of +5 dBm and reduces to 120 mW during power backoff.

Tunable CMOS Integrated Duplexer With Antenna Impedance Tracking and High Isolation in the Transmit and Receive Bands

A hybrid transformer-based integrated tunable duplexer is demonstrated. High isolation between the transmit and receive ports is achieved through electrical balance between the antenna and balance network impedances. A novel high-power-tolerant balance network, which can be tuned at both the transmit and receive frequencies, allows high isolation in both the transmit and receive bands even under realistic antenna impedance frequency dependence. To maintain high isolation despite antenna impedance variation, a feedback loop is employed to measure the transmitter leakage and correct the impedance of the balance network. An isolation > 50 dB in the transmit and receive bands with an antenna voltage standing-wave ratio within 2:1 was achieved. The duplexer, along with a cascaded direct-conversion receiver, achieves a noise figure of 5.3 dB, a conversion gain of 45 dB, and consumes 51 mW of power. The insertion loss in the transmit path was less than 3.8 dB. Implemented in a 65-nm CMOS process, the chip occupies an active area of 2.2 mm2.

Integrated RF Interference Suppression Filter Design Using Bond-Wire Inductors

Design techniques are presented for the realization of high-performance integrated interference suppression filters using bond-wire inductors. A new configuration is proposed for mitigating the impact of mutual coupling between the bond wires. A differential low-noise amplifier with an integrated on-chip passive interference suppression filter is designed at 2.1 GHz in a 0.18-mum CMOS process, and achieves a transmit leakage suppression of 10 dB at 190-MHz offset. The differential filter uses metal-insulator-metal capacitors and bond-wire inductors and occupies only 0.22 mm2. The cascaded system achieves a measured gain of 9.5 dB with a 1.6-dB noise figure and -5 dBm out-of-band IIP3 and consumes 11 mA from a 2-V supply.

Digital-IF WCDMA handset transmitter IC in 0.25-μm SiGe BiCMOS

Implemented in a 0.25-μm SiGe BiCMOS process, a highly integrated low-power transmitter IC (TxIC) is developed for wideband code-division multiple-access handset applications. Based on a digital-IF heterodyne architecture, it eliminates the external IF surface acoustic wave filter by adopting a meticulous frequency plan and a special-purpose second-order-hold D/A conversion scheme. The TxIC features a low-power high-speed D/A converter designed to drive a dominantly capacitive load. For the upconversion mixer and the RF amplifier, adaptive biases are designed to minimize the quiescent power consumption and to provide current boost only when needed. The TxIC achieves <1% EVM. It consumes 180 mW (3-V supply) for the maximum output power of +5 dBm and reduces to 120 mW during power backoff.

An Active Transmitter Leakage Suppression Technique for CMOS SAW-Less CDMA Receivers

A CDMA-2000 receiver without interstage RF SAW filter is presented. An active bandpass sink filter is proposed to selectively filter the transmitted leakage after the downconversion mixer. The impact on receiver noise and linearity performances is discussed. This technique improves the triple-beat (TB) and IIP2 of the receivers by 6.5 dB each, at the expense of a small increase in DC current and noise. Designed in 0.18 μm CMOS technology, the receiver achieves 45 dB gain with uncalibrated IIP2 of +46 dBm and triple-beat of 69 dB.

A SAW-less CDMA receiver front-end with single-ended LNA and single-balanced mixer with 25% duty-cycle LO in 65nm CMOS

A fully integrated SAW-less direct conversion CDMA receiver with single-ended LNA and modified single-balanced passive mixer is manufactured in a 65 nm digital CMOS process. The measured receiver gain at 1.96 GHz was 37 dB, NF was 3 dB, IIP2 was +62 dBm, and cross-modulation triple beat (TB) was 65 dB.