Hirofumi Isomura

All-digital ADC/TDC using TAD architecture for highly-durable time-measurement ASIC

For achieving a highly-durable auto-lidar (light detection and ranging) time-measurement ASIC, an all-digital ADC/TDC using a time-domain processor TAD (Time A/D converter) is presented. In order to realize wide-range temperature durability, sensor ADC/TDC circuits should be fully-digital, including a ring-delay-line (RDL) driven by an input voltage Vin for its power supply, along with an RDL frequency counter, latch and encoder. In this study, ADC/TDC cores are implemented with 0.26/0.35mm2, respectively, in a low-cost 0.35-μm digital CMOS by applying the same circuit architecture TAD. When the received pulse signal level is high, a 4-input terminal TDC can be used to directly digitize the round-trip time of light pulses with time-resolution 244ps/LSB (13-bit) without any AGC techniques. On the other hand, when detecting very-low-level noisy signals received, a high-speed ADC with voltage-resolution 10.9 mV/LSB (6.5bit, 40MS/s) is available for integrating received pulse amplitude to determine signal-travel time in a wide temperature range between -40 and 125°C. Finally, using the all-digital ADC/TDC, a time-measurement ASIC in a 0.35-μm CMOS for low-cost auto lidar has been developed, adapting to variable received-signal levels.

All-Digital A/D converter TAD for sensor interface over wide temperature ranges

For achieving a highly-durable sensor ASIC with high performance and low cost, an all-digital sensor ADC using a time-domain processor TAD (Time A/D converter) is presented. Generally, measuring travel time of signals (e.g., light pulses, radio and ultrasonic waves, etc.) should be done under various stringent conditions (i.e., high ambient temperature) in automobiles, heavy-machinery and resource exploration systems, for example. Therefore, to realize wide-range temperature durability, sensor ADC circuits should be fully-digital, including a ring-delay-line (RDL) driven by an input voltage Vin for its power supply, along with an RDL frequency counter, latch and encoder. In this study, an ADC core is implemented with 0.26 mm2 in a low-cost 0.35-μm digital CMOS applying our original 2-CKES (clock edge shift) method for higher resolution. When detecting low-level noisy signals received, a high-speed sensor ADC with a voltage resolution of 10.9 mV/LSB (6.5bit, 40MS/s) is available for integrating received pulse/wave amplitude to determine signal-travel time in a wide temperature range between -40 and 125°C. In addition, the all-digital architecture TAD is suitable for porting and scaling to another silicon technology with minimal IC design term and cost. As a scaling result, using a test-IC in a 0.18-μm digital CMOS, we have also experimentally confirmed its stable operations between -40 and 125°C with a smaller active area (0.044mm2) and higher resolutions, resulting in 0.15mV/LSB (1MS/s).