Takamoto Watanabe

An all-digital analog-to-digital converter with 12-/spl mu/V/LSB using moving-average filtering

A compact, high-resolution analog-to-digital converter (ADC) especially for sensors is presented. The basic structure is a completely digital circuit including a ring-delay-line with delay units (DUs), along with a frequency counter, latch, and encoder. The operating principles are: (1) the delay time of the DU is modulated by the analog-to-digital (A/D) conversion voltage and (2) the delay pulse passes through a number of DUs within a sampling (= integration) time and the number of DUs through which the delay pulse passes is output as conversion data. Compact size and high resolution were realized with an ADC having a circuit area of 0.45 mm/sup 2/ (0.8-/spl mu/m CMOS) and a resolution of 12 /spl mu/V (10 kS/s). Its nonlinearity is /spl plusmn/0.1% FS per 200-mV span (1.8-2.0 V), for 14-b resolution. Sample holds are unnecessary and a low-pass filter function removes high-frequency noise simultaneously with A/D conversion. Thus, the combination of this ADC and a digital filter that follows can eliminate an analog prefilter to prevent the aliasing before A/D conversion. Also, both this ADC can be shrunk and operated at low voltages, so it is an ideal means to lower the cost and power consumption. Drift errors can be easily compensated for by digital processing.

An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time

An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (2/sup 5/ inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. In a prototype integrated circuit (IC) using 0.65-/spl mu/m CMOS, the generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock with seven reference clocks, for a high-speed response. The cell size was 1.08 /spl times/ 1.08 mm/sup 2/, and the output clock frequency had a wide range of 50 kHz/spl sim/60 MHz. The multiplication range of the clock frequency was also a very wide 4/spl sim/1022, and a high level of precision was achieved with a clock jitter standard deviation of 234 ps. This digital PLL can withstand a broad range of operating environments, from -30/spl deg/C/spl sim/140/spl deg/C, and is suitable for making a programmable clock generator on a chip.

An all-digital ADC/TDC for sensor interface with TAD architecture in 0.18-µm digital CMOS

An analog-to-digital and time-to-digital converter using a common architecture (Time A/D converter TAD) is presented. Its resolutions for both analog-to-digital converter (ADC) mode and time-to-digital converter (TDC) mode are settable. The circuit structure is a completely digital circuit including a ring-shaped pulse-delay-line (RDL) driven by an input voltage Vin, along with an RDL synchronous counter, latch, and encoder. A prototype TAD-IC core of 0.044 mm2 in a 0.18-µm digital CMOS achieved 3.1 mV/LSB (8-bit, 20-MS/s, 1.7 mW), 15 µV/LSB (16-bit, 100-kS/s, 1.3 mW) in ADC mode, and 126 ps/LSB (Vin = 1.8 V, 25-bit), 368 ps/LSB (Vin = 1.0 V, 25-bit) in TDC mode, respectively. As an actual example of high-resolution ADC, a radio-controlled clock (RCC) receiver IC prototype is implemented with a minimum detectable sensitivity of 0.7 µVrms.

All-Digital Quadrature Detection With TAD for Radio-Controlled Clocks/Watches

Time analog-to-digital converters (TADs) based on the power-supply voltage dependence of CMOS gate propagation delay time can be constructed solely of CMOS digital circuits and are characterized by output of the time integral of input voltage, with no dead time. This paper describes digital quadrature detection (DQD) by TAD (TAD-DQD). With TAD-DQD, the in-phase and quadrature components of the input signal, including amplitude and phase information, can be obtained simply by adding and subtracting AD-converted TAD output using a sampling frequency that is four times the carrier frequency of the target signal. As an example of the application of TAD-DQD, the standard-time and frequency-signal receiver circuits of a radio-controlled clock/watch are shown, and the experimental results demonstrate that the time code can in fact be received.

An RCC receiver IC with TAD-DQD and ADPLL using frequency multiplying number with decimals

A 0.18-mum CMOS RCC (radio-controlled clock) receiver IC with TAD (Time A/D converter) and ADPLL was realized. This IC, which receives low-frequency (LF) standard time waves, performs AM detection with digital circuits. It has two key components. First, TAD is an all-digital analog-to-digital converter, whose voltage resolution is settable (15 muV/LSB at 100 kS/s and 3.1 mV/LSB at 20 MS/s). Second, the ADPLL applying a frequency multiplying number of 4.8828125 generates a 160 kHz ADC (TAD) sampling clock from a 32.768 kHz quartz-clock for digital detection processing. The DSP section, which operates as an adder-subtractor and digital filters, consists of standard cells (75,000 gates). This test IC achieved minimum detectable sensitivity of 0.7 muVrms and maximum detectable sensitivity of 100 mVrms for a standard time wave of 40 kHz at the LNA input terminal. Since the TAD sampling frequencies are settable with desirable multiplying numbers with decimals, the IC can receive different kinds of LF standard time waves such as 40 kHz (JP), 60 kHz (JP), 77.5 kHz (DE), and 68.5 kHz (CN) without any use of quartz-crystal filters.

An all-digital A/D converter TAD with 4-shift-clock construction for sensor interface in 0.65-μm CMOS

TAD (Time A/D converter)-composite architecture with 4-shift-clock construction for both fast conversion and increased resolution is presented. An all-digital A/D converter using TAD architecture includes the following: 1) a ring-delay-line (RDL), that is a loop inverter chain, with 16 delay units (DUs), in which delay times are modulated by an A/D conversion voltage Vin for the DU supply voltage; 2) pulse latches; 3) an encoder; and 4) an RDL-frequency counter. The operating principle is to count the number of DUs through which the pulse passes within a sampling time interval Ts with (1/4)LSB-offset for 4-TAD-module by applying a new method named “Clock-Edge-Shift construction (CKES)” to achieve ADC speed-up and resolution-improvement effectively. The 15-bit TAD ADC with 1.2 mm2 using a 0.65-μm CMOS achieved both 2.9 mV/LSB at 10 MS/s and 5.7 mV/LSB at 20 MS/s, respectively, by applying the CKES construction with 4-TAD-composite core, resulting in the same level as 0.25-μm digital CMOS performance.

An all-digital PLL using frequency multiplying/dividing number with decimals in 0.18-μm digital CMOS

An all-digital PLL that generates arbitrary output clock frequencies with only one reference clock frequency is presented. The method adopted in this study uses multiplying/dividing numbers with decimals. A ring-delay-line (RDL) consisting of 32 stages makes it possible for both the frequency detector and digitally-controlled oscillator to have a common time base, resulting in this unique clock generator. Evaluation experiments were conducted using a 0.18-mum CMOS test chip of 0.096 mm2. In the case of a reference clock frequency of 60 kHz and multiplying number of 16.666, we confirmed a 999.96 kHz output clock with 11.6 ppm frequency error and 540 ps jitter standard deviation.

High-Resolution Magneto-Impedance Sensor With TAD for Low Noise Signal Processing

We propose a new measurement system using a magnetoimpedance (MI) sensor with a time analog-to-digital (TAD) converter for a very weak magnetic field measurement and for a low noise signal processing. To demonstrate magnetic characteristics of the proposed measurement system of MI sensor with TAD, we measured the magnetic field sensitivity of the new MI sensor measurement system. In addition, we also investigated the noise level of this proposed measurement system owing to verification on the possibility of the detection of very weak magnetic signals. The gradiometer of MI sensor with TAD was applied to reduce extrinsic noise, such as geomagnetism and commercial power supply noise. We demonstrated that the newly developed MI sensor measurement system has 3 pT/LSB resolution without an amplifier. This shows that the proposed measurement system of MI sensor with TAD is suitable for a low-noise measurement.

A 0.0027-mm 2 9.5-bit 50-MS/s all-digital A/D converter TAD in 65-nm digital CMOS

An all-digital A/D converter TAD (Time A/D converter) with 0.0027 mm2 is presented. The circuit structure is completely digital including a pulse-delay-line driven by Vin (input voltage), along with a counter, latch, and encoder. The TAD is easily shrinkable with the advancement in CMOS process technologies without any change of circuit architecture. Thanks to this construction, A/D conversion resolution with TAD method can automatically be improved. Their voltage resolutions of design rules from 0.8 µm to 65 nm are experimentally confirmed and compared, resulting in 80 times higher resolution of 65-nm TAD than that of 0.8-µm TAD. At the same time, the TAD core size is reduced less than 1/100. The unique TAD feature is that its resolution is settable by selecting sampling rates and power consumption is very low. For example, a prototype IC with 65-nm digital CMOS with 1.2-V supply voltage achieved 18.4-bit at 100-kS/s (1.11 mW), 10.8-bit 20-MS/s (1.13 mW), and 9.5-bit 50-MS/s (1.18 mW), respectively.

A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS

Using the example of an air bag controller, a single chip solution for automotive sub-control systems is investigated, by using a technological combination of improved circuits, bipolar complimentary metal oxide silicon double-diffused metal oxide silicon (BiCDMOS) and thick silicon on insulator (SOI). For circuits, an automotive specific reduced instruction set computer (RISC) center processing unit (CPU), and a novel, all integrated system clock generator, dividing digital phase-locked loop (DDPLL) are proposed. For the device technologies, the authors use SOI-BiCDMOS with trench dielectric-isolation (TD) which enables integration of various devices in an integrated circuit (IC) while avoiding parasitic miss operations by ideal isolation. The structures of the SOI layer and TD, are optimized for obtaining desired device characteristics and high electromagnetic interference (EMI) immunity. While performing all the air bag system functions over a wide range of supply voltage, and ambient temperature, the resulting single chip reduces the electronic parts to about a half of those in the conventional air bags. The combination of single chip oriented circuits and thick SOI-BiCDMOS technologies offered in this work is valuable for size reduction and improved reliability of automotive electronic control units (ECUs).