Hirofumi Matsui

A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s

This paper presents a 14-bit digitally self-calibrated pipelined analog-to-digital converter (ADC) featuring adaptive bias optimization. Adaptive bias optimization controls the bias currents of the amplifiers in the ADC to the minimum amount required, depending on the sampling speed, environment temperature, and power-supply voltage, as well as the variations in chip fabrication. It utilizes information from the digital calibration process and does not require additional analog circuits. The prototype ADC occupies an area of 0.5/spl times/2.3 mm/sup 2/ in a 0.18-/spl mu/m dual-gate CMOS technology; with a power supply of 2.8 V, it consumes 19.2, 33.7, 50.5, and 72.8 mW when operating at 10, 20, 30, and 40 MS/s, respectively. The peak differential nonlinearity (DNL) is less than 0.5 least significant bit (LSB) for all the sampling speeds with temperature variation up to 80/spl deg/C. When operated at 20 MS/s with 1-MHz input, the ADC achieves 72.1-dB SNR and 71.1-dB SNDR.

A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration

A new digital distortion calibration technique is demonstrated in a 14-bit 20-MS/s pipelined analog-to-digital converter (ADC). Calibration parameters are obtained in a way similar to conventional digital gain calibration. The prototype ADC has been fabricated in a 0.18-mum CMOS process and consumes 33.7 mW at 2.8 V. Using the proposed calibration method, a 15-dB improvement of the third-order harmonic rejection is achieved. The measured SNDR and SFDR are 71.6 and 82.3 dB, respectively

A 14bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40MS/s

A 14bit digitally self-calibrated pipelined ADC featuring the adaptive bias optimization is fabricated in a 0.18/spl mu/m dual-gate CMOS and consumes 19.2, 33.7, 50.5 and 72.8mW respectively when operating at 10, 20, 30 and 40MS/s. In all the operating speeds with temperature variation up to 80/spl deg/C, DNL is kept between /spl plusmn/0.60LSB. When operating at 20MS/s, it achieves 73.2dB SNR and 70.4dB SNDR.

1.25Gbps optical links for mobile handsets

This paper presents a 1.25 Gbps optical links design for mobile handsets. The system consists of an optical connector and a SER/DES main chip. The former contains an 850 nm VCSEL (vertical cavity surface emission laser), a GaAs-PIN photodiode and a transimpedance amplifier (TIA). The later includes a serializer, a deserializer, a VCSEL driver, a limiting amplifier, a PLL and a CDR. The chip and TIA were fabricated in a 0.13 um CMOS process with MIM capacitors. A digital type CDR with fine timing controls allows sharing a VCO between transmitter and receiver, resulting in reduced both power consumption and silicon area. The system fully demonstrated a 1.25 Gbps data and video stream transmission, consuming 108.4 mW of power under 1.2 V/3.3 V supply voltages.