Kunihiko Iizuka

A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s

This paper presents a 14-bit digitally self-calibrated pipelined analog-to-digital converter (ADC) featuring adaptive bias optimization. Adaptive bias optimization controls the bias currents of the amplifiers in the ADC to the minimum amount required, depending on the sampling speed, environment temperature, and power-supply voltage, as well as the variations in chip fabrication. It utilizes information from the digital calibration process and does not require additional analog circuits. The prototype ADC occupies an area of 0.5/spl times/2.3 mm/sup 2/ in a 0.18-/spl mu/m dual-gate CMOS technology; with a power supply of 2.8 V, it consumes 19.2, 33.7, 50.5, and 72.8 mW when operating at 10, 20, 30, and 40 MS/s, respectively. The peak differential nonlinearity (DNL) is less than 0.5 least significant bit (LSB) for all the sampling speeds with temperature variation up to 80/spl deg/C. When operated at 20 MS/s with 1-MHz input, the ADC achieves 72.1-dB SNR and 71.1-dB SNDR.

A 184 mW Fully Integrated DVB-H Tuner With a Linearized Variable Gain LNA and Quadrature Mixers Using Cross-Coupled Transconductor

A fully integrated direct conversion DVB-H tuner is realized in a 0.5-mum SiGe BiCMOS technology. To meet the stringent linearity requirement while keeping low power consumption, novel linearization techniques for a variable-gain low-noise amplifier (VG-LNA) and a mixer are proposed. The proposed linearized VG-LNA has a variable gain range of over 50 dB, noise figure of less than 2.6 dB over the frequency range from 200 to 1000 MHz, and IIP3 of more than -10 dBm at a current consumption of 2.1 mA. The quadrature mixer with the proposed linearization technique achieves OIP3 of more than 25 dBm at a current consumption of 5 mA. In addition, a new offset-cancel feedback is introduced for the baseband block of a direct conversion receiver, which keeps the high-pass cutoff frequency independent of the baseband VGA gain. The fabricated tuner IC satisfies all the DVB-H requirements at a power consumption of 184 mW

A digital terrestrial television (ISDB-T) tuner for mobile applications

A 160mW low-IF single-chip tuner for a mobile ISDB-T receiver is realized in SiGe BiCMOS. Its 25mW variable gain LNA shows 2.7dB NF and 62dB variable gain range. The 20mW switched-capacitor channel selection filter exhibits 80dB out-of-band rejection and 11nV//spl radic/Hz input referred noise.

A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration

A new digital distortion calibration technique is demonstrated in a 14-bit 20-MS/s pipelined analog-to-digital converter (ADC). Calibration parameters are obtained in a way similar to conventional digital gain calibration. The prototype ADC has been fabricated in a 0.18-mum CMOS process and consumes 33.7 mW at 2.8 V. Using the proposed calibration method, a 15-dB improvement of the third-order harmonic rejection is achieved. The measured SNDR and SFDR are 71.6 and 82.3 dB, respectively

A 23 mW 256-tap 8 MSample/s QPSK matched filter for DS-CDMA cellular telephony using recycling integrator correlators

In direct sequence code division multiple access (DS-CDMA), matched filters calculate the cross-correlation function of a received signal spread by a pseudo-random noise (PN) sequence and a replica PN sequence. A matched filter like this can be viewed as a finite impulse response (FIR) filter with a PN sequence used as the binary tap weights, minimizing search and synchronization times in DS-CDMA receivers. This paper introduces an approach for implementing matched filters based on recycling integrator correlators (RICs) that use a sensible combination of analog and digital processing to minimize area and power consumption. The matched filter is organized by combining an array of RICs, a cyclic shift register which stores a PN sequence, and a rotary multiplexer which transfers the correlation values one by one. This implementation provides: 1) an input analog signal processing capability without the need of a fast ADC; 2) an already digitally-coded output stream; 3) small capacitor ratios for the switched-capacitor (SC) integrators; and 4) minimum die-area and current consumption for the available technology and the spreading ratio, that is, the length of the PN sequence. The fabrication process is a 0.35 /spl mu/m CMOS double-metal, double-poly process. The chip occupies 22.8 mm/sup 2/ and dissipates 23 mW with a 1.8 V power supply.

Capacitively coupled non-contact probing circuits for membrane-based wafer-level simultaneous testing

Wafer-level simultaneous testing (WLST) where all chips on a wafer are tested and burned in at the same time is preferable in reducing the cost of obtaining Known Good Dies (KGDs). At present, however, it is difficult to realize the WLST because it requires a probe card with some hundred thousand needles, leading to more than a ton of force needed for stable contact of all needles. Non-contact probing has been proposed based on a chip-to-chip inductively-coupled interface [1] which can reduce the force but it needs a probing chip built specific to a certain product, which is costly. Recently, a low-cost membrane-based probing technique has been disclosed which makes use of the atmospheric pressure and 700kg of force can be uniformly distributed over a 300mm wafer [2]. Yet, since a contacting bump is used and each bump requires 4g of force, the number of pins is limited to about 150K, which is still the world biggest pin counts ever reported.

A 14bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40MS/s

A 14bit digitally self-calibrated pipelined ADC featuring the adaptive bias optimization is fabricated in a 0.18/spl mu/m dual-gate CMOS and consumes 19.2, 33.7, 50.5 and 72.8mW respectively when operating at 10, 20, 30 and 40MS/s. In all the operating speeds with temperature variation up to 80/spl deg/C, DNL is kept between /spl plusmn/0.60LSB. When operating at 20MS/s, it achieves 73.2dB SNR and 70.4dB SNDR.

Embedded anti-aliasing in switched-capacitor ladder filters with variable gain and offset compensation

A combination of continuous-time and switched capacitor integrators in a simulated LC lossless ladder yields a response with suppressed aliasing without the use of continuous-time prefiltering. Fabricated in a 0.35-/spl mu/m CMOS process, a fifth-order Cauer low-pass filter for a W-CDMA cellular phone receiver has a cutoff frequency of 1.92 MHz and aliasing suppression of better than 40 dB for 30.72-MHz sampling. Without using any tuning mechanism, a 10% accuracy of the cutoff frequency is achieved. As additional features, the filter has variable gain from -13.3 to 16.4 dB and an offset compensation mechanism. With the latter, a 50-mV dc offset added to the input is suppressed to 11 mV or less at the filter output under the maximum gain setting. The filter consumes 2.81 mA at 1.8-V power supply in a die area of 0.62 mm/sup 2/.

A 184mW Fully Integrated DVB-H Tuner Chip with Distortion Compensated Variable Gain LNA

A single chip direct conversion DVB-H tuner with a distortion compensated variable gain LNA is implemented in 0.5mum SiGe BiCMOS. The LNA exhibits 0dBm IIP3 and 2.8dB NF at 860MHz. A new offset cancel feedback is introduced that keeps the cutoff frequency independent of the baseband gain. The IC consumes 184mW at 2.8V while achieving a sensitivity of -96dBm for QPSK, CR=1/2 signal

CMOS Biosensor IC Focusing on Dielectric Relaxations of Biological Water With 120 and 60 GHz Oscillator Arrays

In this paper, a CMOS biosensor integrated circuit (IC) focusing on dielectric relaxations of biological water with 120 and 60 GHz oscillator arrays is proposed. To realize label-free biosensing, we focus on frequencies around 100 GHz where changes in the dielectric constant of water become prominent as many a water molecule is bound to biomolecules. To detect the state of the biological water, sensing elements based on LC-oscillators operating at 120 and 60 GHz are realized using the 65 nm CMOS process. The sizes of the sensing elements are significantly smaller than the wavelengths of the operating frequencies, therefore 2-D arrays can be implemented in a chip. The trial chip enables us to obtain spatial distributions of the targets. In this paper, the cultivated bacterial colony growth is monitored and other biosensing applications are explained, which showcase possibilities for using the biosensor IC.