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Dive into the research topics where Hirohito Mukai is active.

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Featured researches published by Hirohito Mukai.


ieee radar conference | 2013

Advanced millimeter-wave radar system using coded pulse compression and adaptive array for pedestrian detection

Takaaki Kishigami; Kiyotaka Kobayashi; Maiko Otani; Tadashi Morita; Hirohito Mukai; Asako Saito; Yoichi Nakagawa

This paper reports a radar system design using millimeter-wave for vehicular and pedestrian safety around intersections. The proposed system design and associated key algorithms are embedded into a prototype and verified in an anechoic chamber and a trial intersection. The system covers 30 cm range resolution, 5-degree angle resolution, 95% detection rate and 10% false alarm rate. The results therefore prove the system feasibility for future automotive safety application.


asia pacific microwave conference | 2012

Advanced code sequences design for pedestrian detection in millimeter-wave pulse-compression radar system

Kiyotaka Kobayashi; Tadashi Morita; Hirohito Mukai; Takaaki Kishigami; Yoichi Nakagawa

The paper proposes code sequences with an optimized criterion for precisely detecting pedestrians in the presence of vehicles in millimeter-wave pulse-compression radar system. The criterion named FR (Floor-Ratio) focuses on the maximum of sidelobes. The code sequences based on FR attain higher maximum sidelobe suppression compared to the ones based on conventional criterion. Computer simulation and experimental measurement have been done for verification. Consequently, our work proves the effectiveness of the proposed code sequences with the criterion for next generation millimeter-wave radar systems.


IEEE Transactions on Microwave Theory and Techniques | 2015

A Reconfigurable 50-Mb/s-1 Gb/s Pulse Compression Radar Signal Processor With Offset Calibration in 90-nm CMOS

Jun Li; Mehmet Parlak; Hirohito Mukai; Michiaki Matsuo; James F. Buckwalter

This paper presents a reconfigurable mixed-signal-processing circuit for high-speed pulse compression radar (PCR). Mixed-signal design techniques incorporate calibration and adaptation to improve the performance of a PCR receiver. Adaptive bandwidth PCR is an important feature for maximizing the dynamic range of a low-power radar system. The baseband signal processor includes a variable gain amplifier, 4-bit digital-to-analog converter, high-speed analog correlator, passive integrator, a 4-bit flash analog-to-digital converter, and a multi-range delay-locked loop. This proposed system is fabricated in 90-nm CMOS and can be configured to work from 50 Mb/s to 1 Gb/s with 2/3/5/7-bit Barker codes. The proposed calibration techniques improve the sidelobe reduction to 15.6 dB at 1 Gb/s. The total power consumption is 42 mW at the peak rate of 1 Gb/s for 15-cm range resolution.


asia pacific microwave conference | 2012

Millimeter-wave radar combining Tx beamforming and Rx array processing for precise pedestrians detection

Takaaki Kishigami; Tadashi Morita; Hirohito Mukai; Yoichi Nakagawa

The advanced radar detection method which combines Tx beamforming and Rx array processing with highresolution direction of arrival (DOA) estimation is proposed. The proposed method associates DOA estimation direction with Tx beamforming direction (TxD-DOA) for a high accuracy detection for multiple targets in millimeter-wave radar system. Computer simulation and experiment evaluation verify the improvement effects of the TxD-DOA method. We have confirmed that the suppression of multiple radar reflection waves by the transmission beam scanning brings the better DOA estimation accuracy and higher angular resolution of the TxD-DOA for multiple human targets.


custom integrated circuits conference | 2013

A 1Gb/s reconfigurable pulse compression radar signal processor in 90nm CMOS

Jun Li; Hirohito Mukai; Mehmet Parlak; Michiaki Matsuo; James F. Buckwalter

This paper presents a reconfigurable analog signal processing circuit for pulse compression radar. Adapting bandwidth for the range of the target is proposed for radar systems. The baseband signal processor includes a high-speed correlator/integrator, a 4-bit flash analog-to-digital converter (ADC) and a multi-range delay lock loop (DLL). The DLL generates multi-phase clock to align the template signal with the received signal. The circuit is fabricated in 90-nm CMOS and can be configured to work from 50Mb/s to 1Gb/s with Barker codes. A sidelobe reduction (SLR) of 15.6dB is demonstrated for 1Gb/s. The total power consumption is 33mW at 1Gb/s.


Archive | 2009

Base station device and distance measuring method

Takashi Fukagawa; Yasunari Kimura; Yoichi Nakagawa; Hirohito Mukai


Archive | 2014

Phased array transmission device

Michiaki Matsuo; Junji Sato; Hirohito Mukai


Archive | 2010

Radio terminal device, radio base station device, radio ranging system, and radio ranging method

Hirohito Mukai; Takashi Fukagawa; Yoichi Nakagawa


Archive | 2009

WIRELESS DISTANCE MEASUREMENT SYSTEM AND WIRELESS DISTANCE MEASUREMENT METHOD

Takashi Fukagawa; Hirohito Mukai; Yoichi Nakagawa; Tadao Inoue


Archive | 2009

Radio positioning system and coordinate configuring method

Hirohito Mukai; Takashi Fukagawa; Yoichi Nakagawa; Toshiki Kanehara

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