Hiroki Mizosoe

A Single Chip H.264/AVC HDTV Encoder/Decoder/Transcoder System LSI

A new single chip HDTV H.264 codec system LSI was designed using flexible codec architecture. It supports HP@L4.1 with full 1920x1080 resolution. The LSI supports MPEG2 and JPEG as well. The chip integrates one encoder and two decoders, which work independently and can be used in flexible ways including transcoding. It also integrates almost all the necessary functions for digital consumer application including an audio codec, graphics and video circuitry, peripherals, and a generic microprocessor.

An advanced multimedia processing LSI suitable for HDTV applications

We have newly developed a multimedia processing LSI, targeting HDTV applications such as a digital broadcasting receiver based on ATSC or ARIB standards. It integrates many essential features such as multiple HDTV/SDTV input and output ports, an MPEG2-I/JPEG decoder, programmable video scaling engines, alpha-blending and a 2-D graphic engine. The chip can also achieve a multi-image display function by combining the elementary functions discussed. This LSI will be very useful in a broad range of multimedia applications such as DTV/ATV receivers, set top boxes, interactive TVs, cables and satellites.

Very low-delay H.264 codec for consumer applications

We have newly developed a very low-delay full HD codec with relatively lower bitrate focusing especially on consumer or small business applications. We have analyzed several important factors for achieving low-delay, and developed a new codec pipeline control scheme for our versatile H.264 codec platform already developed. We implemented the algorithm on the codec platform, and obtained a result of 10 ms minimum delay with several test sequences at bitrate of 8 to 10 Mbps.

An 80 mm/sup 2/ MPEG2 audio/video decode LSI

This compact, single chip MPEG-2 audio/video decoder performs all necessary signal processing required for digital satellite TV and cable television (CATV) receivers based on the main profile at main level (MPEG-2 MP@ML) standard. This decoder uses 135,000 gates (2-input NAND equivalents) and occupies 8.6/spl times/9.3 mm/sup 2/ in a triple-layer-metal, 0.5 /spl mu/m CMOS standard-cell process and is much smaller than any MPEG-1/MPEG-2 decoder previously reported.

Highly Efficient H.264/AVC Codec Technology for High Definition Consumer Applications

This paper presents newly developed highly efficient H.264 codec technologies for high definition consumer products. An essential set of H.264 coding tools has been determined as a result of an image evaluation. In addition, a new binary arithmetic decoding algorithm was developed in order to achieve necessary performance on the minimal sufficient clock frequency. These algorithms were implemented in our new H.264/AVC high definition codec LSI targeting mobile digital appliances including an HD camcorder.