Hironori Komi

Very low-delay H.264 codec for consumer applications

We have newly developed a very low-delay full HD codec with relatively lower bitrate focusing especially on consumer or small business applications. We have analyzed several important factors for achieving low-delay, and developed a new codec pipeline control scheme for our versatile H.264 codec platform already developed. We implemented the algorithm on the codec platform, and obtained a result of 10 ms minimum delay with several test sequences at bitrate of 8 to 10 Mbps.

An MPEG2/4 dual codec with sharing motion estimation

An MPEG2/4 dual codec algorithm has been developed, targeting consumer products with digital video storage, digital network communication, and so on. By using new method of sharing the motion estimation (ME) between MPEG2 and MPEG4, a low power and high quality MPEG2/4 dual codec system can be achieved.

Analysis of cache efficiency in 2D wavelet transform

In software implementations of image processing algorithms, efficient cache utilization is one of the most important factors to accomplish high performance microprocessor computing. In this paper, we propose a cache efficient block-based wavelet decomposition procedure and provide an analysis for the 2D wavelet transform. The wavelet transform is the core algorithm for the JPEG2000 compression standard, which can achieve higher compression ratio than the original JPEG standard while not suffering from the block boundary artifacts that appear at low rates when a DCT based algorithm such as JPEG is used. On the other hand, wavelet transform is a memory consuming algorithm and it turns out that many cache misses occur in the microprocessor computation process. This paper introduces a theoretical analysis to predict the most cache effective block-size to be used, given the cache size and image sizes. The simulation results achieved with a microprocessor architecture simulator confirm the cache efficiency predictions obtained with our theoretical analysis.

A low cost noise reduction technology for compressed video

A low cost noise reduction technology for compressed video such as the mosquito noise and the block noise has been developed. The authors characterized the length of filter taps for block and mosquito noise and proposed the memory sharing architecture for both types of noise detection. The architecture contributes the reduction of line memories required for buffering filtering data in a noise reduction pipeline.

System Architecture of H.264/AVC Codec LSI for Digital HD Camcorder

A single chip H.264/AVC codec LSI was newly developed for digital HD camcorder, which integrates a video codec, an audio codec, graphics, video interfaces, peripherals, a host processor, and an SDRAM interface. In order to realize low-power real-time receding and playing back system, the LSI uses a software-based codec architecture and a flexible SDRAM control architecture.