Hiromi Hiraishi

Verification of the Futurebus+ Cache Coherence Protocol

We used a hardware description language to construct a formal model of the cache coherence protocol described in the IEEE Futurebus+standard. By applying temporal logic model checking techniques, we found errors in the standard. The result of our project is a concise, comprehensible and unambiguous model of the protocol that should be useful both to the Futurebus+Working Group members, who are responsible for the protocol, and to actual designers of Futurebus+boards.

Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity

Firstly in this paper, we propose a branching time logic BRTL (Branching time Regular Temporal Logic) which has automata connectives as temporal operators. BRTL is more expressive than CTL proposed by Clarke et.al. and it is modest in terms of model checking, i.e. it has a model checking algorithm which runs in time proportional both to the size of a given Kripke structure and to the length of a given formula, as shown in the paper.

Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification

The major goal of this paper is to clarify how large and practical sequential machines can be verified with the current most powerful supercomputers. The basic algorithm used is an implicit symbolic model checking algorithm, which is shown to be 100 times and 40 times more efficient in time and space than the conventional symbolic model checking algorithms. Based on the algorithm, a vectorized symbolic model checking algorithm, which is suitable for execution on vector processors, is also proposed. Some benchmark results show that it achieves about 6 ∼ 20 acceleration ratio and it can verify a 16 bit pipelined ALU with 4 word register file, which supports 16 arithmetic/logical operations, in around 12 minutes on a vector processor HITAC S-820/80.

Formal Verification of Speed-Dependent Asynchronous Cicuits Using Symbolic Model Checking of branching Time Regular Temporal Logic

Firstly, we show how to deal with bounded uncertain delays of (speed-dependent) asynchronous circuits for symbolic model checking based on temporal logic. We adopt discrete-time model. In the modeling of uncertain delays, we consider two models, i.e. static delay and dynamic delay. These models are interpreted as parameterized sequential machines and nondeterministic sequential machines respecitively.

Data Compression of the Kanji Character Patterns Digitized on the Hexagonal Mesh

This correspondence describes new two-stage data compression algorithms of Kanji character patterns digitized on the hexagonal mesh. One third of the pattern elements are stored, and an additional small amount of data is used to correct effors in the recovered pattern. A data reduction of 60 percent has been achieved.

Verification of deadlock free property of high level robot control

This paper describes an efficient verification algorithm for deadlock free property of high level robot control called Task Control Architecture (TCA). TCA is a model of concurrent robot control processes. The verification tool we used is the Symbolic Model Verifier (SMV). Since the SMV is not so efficient for verification of liveness properties such as deadlock free property of many concurrent processes, we first described the deadlock free property by using safety properties that SMV can verify efficiently. In addition, we modify the symbolic model checking algorithm of the SMV so that it can handle many concurrent processes efficiently. Experimental measurements show that we can obtain more than 1000 times speed-up by these methods.

regular temporal logic and its model checking problem

Abstract In order to verify logic design formally, the model checking approach based on propositional temporal logics has been proposed and the approach has been successfully applied to verify finite state machines. Although many temporal logics have been exploited as specification languages, some of them do not have enough expressive power to characterize arbitrary behavior of finite state machines, while others have difficulties in finding design errors. Considering these problems, one of the authors proposed regular temporal logic (RTL). RTL is expressively equivalent to the class of regular sets, and it has a simple algorithm for finding errors. RTL cannot describe, however, a property called fairness, which is defined over infinite sequences, because it is defined over finite sequences. In this paper, firstly, we introduce a new temporal logic infinitary regular temporal logic (∞RTL), which is able to describe fairness, and show that its expressive power is equivalent to the class of finite unions of regular sets and ω-regular sets. Secondly, we show how to reduce the formal verification of finite state machines to the model checking problem of ∞RTL and we prove that the complexity of the model checking problem is nonelementary.

Formal verification of self-testing properties of combinational circuits

This paper proposes a method of formal verification of self-testing (ST) property of combinational circuits using logic function manipulation. In this method we show that the problem of verification of ST property can be transformed to satisfiability problem of a decision function formed from characteristic functions of the circuits output code words. Then the problem can be resolved using binary decision diagrams (BDD) efficiently. Experimental results show the effectiveness of the proposed method.

Time-space modal model checking towards verification of bit-slice architecture

The goal of this paper is to propose a new symbolic model checking approach named time-space modal modal checking, which could be applicable to verification of bit-slice microprocessor of infinite bit width and one dimensional systolic array of infinite length. A simple benchmark result shows the effectiveness of the proposed approach.<<ETX>>

Design Verification of a Microprocessor Using Branching Time Regular Temporal Logic

This paper reports about design verification of a real microprocessor using a symbolic model checking algorithm for a variant of branching time temporal logics, i.e. branching time regular temporal logic (BRTL).