Kiyoharu Hamaguchi

Another Look at LTL Model Checking

We show how LTL model checking can be reduced to CTL model checking with fairness constraints. Using this reduction, we also describe how to construct a symbolic LTL model checker that appears to be quite efficient in practice. In particular, we show how the SMV model checking system developed by McMillan [16] can be extended to permit LTL specifications. The results that we have obtained are quite surprising. For the examples we considered, the LTL model checker required at most twice as much time and space as the CTL model checker. Although additional examples still need to be tried, it appears that efficient LTL model checking is possible when the specifications are not excessively complicated.

The Complexity of the Optimal Variable Ordering Problems of Shared Binary Decision Diagrams

A binary decision diagram (BDD) is a directed acyclic graph for representing a Boolean function. BDDs are widely used in various areas which require Boolean function manipulation, since BDDs can represent efficiently many of practical Boolean functions and have other desirable properties. However the complexity of constructing BDDs has hardly been researched theoretically. In this paper, we prove that the optimal variable ordering problem of shared BDDs is NP-complete, and touch on the hardness of this problem and related problems of BDDs.

Efficient construction of binary moment diagrams for verifying arithmetic circuits

BDD-based approaches cannot handle some arithmetic functions such as multiplication efficiently, while Binary Moment Diagrams proposed by Bryant and Chen (1994) provide compact representations for those functions. They reported a BMD-based polynomial-time algorithm for verifying multipliers. This approach requires high-level information such as specifications to subcomponents. This paper presents a new technique called backward construction which can construct BMDs directly from circuit descriptions without any high-level information. The experiments show that the computation time for verifying for n-bit multipliers is approximately n/sup 4/. We have successfully verified 64-bit multipliers of several type in 3-6 hours with 46 Mbyte of memory on SPARCstation 10/51. This result outperforms previous BDD-based approaches for verifying multipliers.

Ordered Quantum Branching Programs Are More Powerful than Ordered Probabilistic Branching Programs under a Bounded-Width Restriction

One of important questions on quantum computing is whether there is a computational gap between the model that may use quantum effects and the model that may not. Researchers have shown that some quantum automaton models are more powerful than classical ones. As one of classical computational models, branching programs have been studied intensively as well as automaton models, and several types of branching programs are introduced including read-once branching programs and bounded-width branching programs. In this paper, we introduce a new quantum computational model, a quantum branching program, as an extension of a classical probabilistic branching program, and make comparison of the power of these two models. We show that, under a bounded-width restriction, ordered quantum branching programs can compute some function that ordered probabilistic branching programs cannot compute.

Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity

Firstly in this paper, we propose a branching time logic BRTL (Branching time Regular Temporal Logic) which has automata connectives as temporal operators. BRTL is more expressive than CTL proposed by Clarke et.al. and it is modest in terms of model checking, i.e. it has a model checking algorithm which runs in time proportional both to the size of a given Kripke structure and to the length of a given formula, as shown in the paper.

Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs

This paper deals with verification of high-level designs, in particular, symbolic comparison of register-transfer-level descriptions and behavioral descriptions. As models of those descriptions, we use state machines extended by quantifier-free first-order logic with equality. Since the signals in the corresponding outputs of such descriptions rarely change simultaneously, we cannot adopt the classical notion of equivalence for state machines. This paper defines a new notion of consistency based on signal-transitions of the corresponding outputs, and proposes an algorithm for checking consistency of those descriptions, up to a limited number of steps from initial states. A simple hardware/software codesign is taken as an example of high-level designs. A C program for digital signal processing called PARCOR filter was compared with its corresponding design given as a register-transfer-level description, which is composed of a VLIW architecture and assembly code. Since this example terminates within approximately 4500 steps, symbolic exploration of a finite number of steps is sufficient to verify the descriptions. Our prototype verifier succeeded in the verification of this example in 31 minutes.

Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification

The major goal of this paper is to clarify how large and practical sequential machines can be verified with the current most powerful supercomputers. The basic algorithm used is an implicit symbolic model checking algorithm, which is shown to be 100 times and 40 times more efficient in time and space than the conventional symbolic model checking algorithms. Based on the algorithm, a vectorized symbolic model checking algorithm, which is suitable for execution on vector processors, is also proposed. Some benchmark results show that it achieves about 6 ∼ 20 acceleration ratio and it can verify a 16 bit pipelined ALU with 4 word register file, which supports 16 arithmetic/logical operations, in around 12 minutes on a vector processor HITAC S-820/80.

Formal Verification of Speed-Dependent Asynchronous Cicuits Using Symbolic Model Checking of branching Time Regular Temporal Logic

Firstly, we show how to deal with bounded uncertain delays of (speed-dependent) asynchronous circuits for symbolic model checking based on temporal logic. We adopt discrete-time model. In the modeling of uncertain delays, we consider two models, i.e. static delay and dynamic delay. These models are interpreted as parameterized sequential machines and nondeterministic sequential machines respecitively.

Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints

For formal verification of large-scale digital circuits, a method using satisfiability checking of logic with equality and uninterpreted functions has been proposed. This logic, however, does not consider specific properties of functions or predicates at all, e.g. associative property of addition. In order to ease this problem, we introduce “equivalence constraint” that is a set of formulas representing the properties of functions and predicates, and check the satisfiability of formulas under the constraint. In this report, we show an algorithm for checking satisfiability with equivalence constraint and also experimental results.

Automatic monitor generation from regular expression based specifications for module interface verification

In order to verify module interfaces, various verification methods have been proposed. This paper focuses on monitor-based verification of module interfaces. Monitor circuits are usually described by hand. This is a very hard task, however, since it requires low-level design of circuits or state machines. If specifications of module interfaces are described in more a comprehensive way, and monitor circuits are generated by the description, we can verify module interfaces more efficiently. In our method, first, we describe specifications of module interfaces in a language based on regular expressions, then construct behavior models from the description. Finally, we generate a monitor circuit. The circuit connects to a verification target to check whether interface behaviors of the target satisfy the specification. If interface behaviors violate the specification, the circuit asserts an error signal. In this paper, we state the method, and show a verification example based on simulation in which FSM state coverage is monitored.