Hiromi Inaba

Parallel multiple electric power conversion system constructed by connecting three power converters

An electric power conversion system constructed by connecting two or more electric power converters in parallel is advantageous for achieving large capacity and standardization. In this paper, the control method for cross current when three power converters are operated is examined, and reexamined as a preferable system construction method.

A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS

A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm2 and 60 mW.

Simple Routing Control System for 10 Gb/s Data Transmission Using a Frequency Modulation Technique

This paper describes a simple routing control system. We propose achieving high-speed data transmission without modifying the data frame configuration. To add a routing control signal, called the “labeling signal” in this paper, to the data frame, we use a frequency modulation technique on the transmitted frame. This means you need not change the data frame when you transmit additional signals. Using a prototype system comprising a field-programmable gate array and discrete elements, we investigate the system performance and devise a method to achieve high resolution. A three-channel routing control for a 10 Gb/s data frame was achieved, which confirms the advantages of the proposed system.

36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector

A 36-Gb/s clock and data recovery (CDR) circuit with a simple passive loop filter is presented. By combining the passive load for output magnitude generation in the phase detector with a passive loop filter, the cutoff frequency and high-frequency response in the loop filter can be controlled independently. The CDR consists of a half-rate decision circuit that provides higher speed operation. To confirm the validity of the proposed topology, we fabricated a 36-Gb/s CDR IC with the 65-nm MOSFET process. It provides an 18-GHz extracted clock (half rate) signal and 18-Gb/s recovered date (1:2DEMUX output). The measured jitter was lower than 1.15 ps rms. The area of chip, including an I/O buffer circuit, was 1 mm2, and the power consumption was 290 mW.

Method controlling two or more sets of PMSM by one inverter on a railway vehicle

If two or more Permanent Magnet Synchronous Motors (PMSM) can be controlled by one inverter, a train can be driven by less energy than the present Induction Motor (IM) drive system. First, this paper proposes a method for simulating the movement of wheels and a vehicle to develop a control method. Next, a method is presented for controlling two or more PMSMs by one inverter.

25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS

A 25-Gb/s half-rate clock and data recovery (CDR) IC using a current-mode logic (CML) buffer circuit with a latch load circuit for delay generation is presented. To achieve low-power operation of the CDR, the latch-load circuit for delay generation is combined with a CML buffer circuit, which provides a wide controllable delay range. This enable a reduction in the number of the CML circuits for delay generation used in the CDR IC. To confirm the validity of the proposed method, we fabricated a 25-Gb/s half-rate CDR IC with the 65-nm CMOS process. The power consumption of the proposed circuit is around half that of the conventional half-rate CDR circuit The area for the core circuits is 0.09 mm2, and the power consumption without output buffers is 96mW.

Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS

We have proposed a transmission system of the additional data by using frequency modulation technique. In a receiver, demodulation characteristics deteriorate according to data speed. In the previous work, we showed the emphasis technique can reduce the degradation in demodulated signal. In this paper, we designed the delay detection circuit on the basis of the detailed analysis. To investigate the proposed circuit, we fabricated the delay detection circuit with emphasis using 65-nm CMOS process. We confirmed the improved linearity in demodulated signal, which indicate our proposed circuit can be applicable to the 10-Gb/s demodulating systems.

A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS

Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-㎚ CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.

Study of three inputs combination reactor of parallel operation systems constructed with multiple electric power converters

Parallel operation systems constructed quickly and inexpensively by combining two or more existing electric power converters have a lot of flexibility. However, it is important to suppress a cross current flows between the electric power converters. This paper proposes a three inputs combination reactor for parallel operation systems composed three electric power converters.

Design method of cross current suppression control for parallel operation system constructed with two electric power converters

Large-capacity parallel operation systems constructed quickly and inexpensively by combining two or more existing electric power converters have a lot of flexibility. However, it is important to suppress the cross current flows between the converters. This can be done by controlling the system while miniaturizing the combination reactor. In this paper we elucidate the suppression performance of various cross current control methods and provide design guidelines for them.