Keiji Kishine

A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF).

A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs

A 2.5-Gb/s monolithic clock and data recovery (CDR) IC using the phase-locked loop (PLL) technique is fabricated using Si bipolar technology. The output jitter characteristics of the CDR can be controlled by designing the loop-gain design and by using the switched-filter PLL technique. The CDR IC can be used in local-area networks (LANs) and in long-haul backbone networks or wide-area networks (WANs). Its power consumption is only 0.4 W. For LANs, the jitter generation of the CDR when the loop gain is optimized is 1.2 ps (0.003 UI). The jitter characteristics of the CDR optimized for WANs meet all three types of STM-I6 jitter specifications given in ITU-T Recommendation G.958. This is the first report on a CDR that can be used for both LANs and WANs. This paper also describes the design method of the jitter characteristics of the CDR for LANs and WANs.

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX

A loop parameter optimization method for a phase-locked loop (PLL) used in wide area networks (WANs) is proposed as a technique for achieving good jitter characteristics. It is shown that the jitter characteristics of the PLL, especially jitter transfer and jitter generation, depend strongly on the key parameter /spl zeta//spl omega//sub n/ (/spl zeta/ is a damping factor and /spl omega//sub n/ is the natural angular frequency of the PLL), and that the optimization focusing on the /spl omega//sub n/ dependence of the jitter characteristics make it possible to comprehensively determine loop parameters and loop filter constants for a PLL that will fully comply with ITU-T jitter specifications. Using the optimization method with the low-jitter circuit design technique, a low-jitter and low-power 2.5-Gb/s optical receiver IC integrated with a limiting amplifier, clock and data recovery (CDR), and demultiplexer (DEMUX) is fabricated using 0.5-/spl mu/m Si bipolar technology (f/sub T/ = 40 GHz). The jitter characteristics of the IC meet all three types of jitter specifications given in ITU-T recommendation G.783. In particular, the measured jitter generation is 3.2 ps rms, which is lower than that of an IC integrated with only a CDR in our previous work. In addition, the pull-in range of the PLL is 50 MHz and the power consumption of the IC is only 0.68 W (limiting amplifier: 0.2 W, CDR (PLL): 0.3 W, DEMUX: 0.18 W) at a supply voltage of -3.3 V and only 0.35 W at a supply voltage of -2.5 V (without output buffers).

A jitter suppression technique for a 2.48832-Gb/s clock and data recovery circuit

This paper describes a jitter suppression technique for a 2.48832-Gb/s clock and data recovery (CDR) circuit that uses a phase-locked loop (PLL). This technique decreases the jitter generation and improves the jitter transfer function. Jitter generation is suppressed by boosting the loop gain in the PLL. A suitable jitter transfer function and jitter tolerance is achieved by using a low-center-frequency (f/sub c/) surface acoustic wave (SAW) filter. The fabricated circuit has low jitter generation [about 2.4 mUI rms (below 1 ps rms)] and a low cutoff frequency of the jitter transfer function (about 500 kHz) as a result of using a SAW filter with a f/sub c/ of 622.08 MHz. The jitter generations are within 5 mUI rms (2 ps rms) for the temperature range of 0 to 90/spl deg/. The circuit exceeds the jitter tolerance specifications in the International Telecommunication Union (ITU-T) recommendation G.958 by more than 30%.

A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit

This paper describes a jitter suppression technique for a 2.48832 Gb/s clock and data recovery (CDR) circuit that uses a phase-locked loop (PLL). This technique improves both the jitter generation and the jitter transfer function. The jitter generation can be suppressed by boosting the loop gain in PLL. A suitable jitter transfer function and jitter tolerance can be achieved by optimizing the characteristics of a surface acoustic wave (SAW) filter. The fabricated circuit had a low jitter generation (about 2.4 mUI rms) and a low jitter transfer function cutoff frequency (about 500 kHz) by using a SAW filter with a center frequency (f/sub c/) of 622.08 MHz. The jitter generations are within f/sub c/ mUI rms for the temperature range between 0/spl deg/C to 90/spl deg/C. The circuit passes the jitter tolerance specification in ITU-T recommendation G.958 by more than 30%.