Hiroo Masuda

Dummy filling methods for reducing interconnect capacitance and number of fills

In recent system-on-chip (SoC) designs, floating dummy metals inserted for planarization have created serious problems because of increased interconnect capacitance and the enormous amount of fill required. We present new methods to reduce the interconnect capacitance and the amount of dummy metals needed. These techniques include three ways of filling: (1) improved floating square fills, (2) floating parallel lines, and (3) floating perpendicular lines (with spacing between dummy metals above and below signal lines). We also present efficient simple formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the traditional regular square method was 13.1%, while that using the methods of improved square fills, extended parallel lines, and perpendicular lines was 2.5%, 2.4%, and 1.1%, respectively. Moreover, the number of necessary dummy metals can be reduced by two orders of magnitude through use of the parallel line method.

Analysis and characterization of device variations in an LSI chip using an integrated device matrix array

For future LSI design technology, the device matrix array (DMA), which can precisely evaluate variation in device parameters within a die, has been developed. The DMA consists of a 14-by-14 array of common units. The unit size is 240 by 240 /spl mu/m, and each unit contains 148 measurement elements (52 transistors, 30 capacitors, 51 resistors, and 15 ring oscillators).For future large-scale integration design technology, the device matrix array (DMA), which precisely evaluates within-die variation in device parameters, has been developed. The DMA consists of a 14-by-14 array of common units. The unit size is 240 by 240 /spl mu/m, and each unit contains 148 measurement elements (52 transistors, 30 capacitors, 51 resistors, and 15 ring oscillators). The element selection and precise measurement are achieved with low parasitic resistance measurement buses and leakage-controlled switching circuits, which allow the measurement accuracy for a transistor, resistor, or capacitor of 90 pA, 11 m/spl Omega/, and 23 aF, respectively, in the 3/spl sigma/ range. The ability to obtain 29 008 samples from a chip enables statistical analysis of the variation in 148 elements of each chip with 240-/spl mu/m spatial resolution. This high resolution and large sample number allows us to precisely decompose the data into systematic and random variation parts with newly developed fourth-order polynomial fitting. Our methodology has been verified using a test chip fabricated by a 130-nm CMOS process with a 100-nm physical gate length and five Cu interconnect layers. In MOSFETs, the random part was dominant and indicated a certain /spl sigma/ value in every chip. In the case of the interconnect layers, the random and systematic parts of the resistance and the capacitance indicated variance fluctuations. By chip, by item, by size, by structure, random or systematic, the /spl sigma/ values of each variation show inconsistency which we believe is attributable to the Cu process. The correlation coefficients of systematic part between device element and ring oscillator frequency shown very high value (0.87-0.98), and those of a random part were low enough (-0.10-0.22) to prove the accuracy of decomposition.

Efficient capacitance extraction method for interconnects with dummy fills

The accuracy of parasitic extraction has become increasingly important for system-on-chip (SoC) designs. In this paper, we present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by the chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that the existence of the interlayer dummy metal fills has more significant influences than the intralayer dummies in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.

Grooved Gate MOSFET

Grooved Gate type MOS FETs which realize a short channel device with high punch-through breakdown voltage and little threshold voltage (VT) fluctuation, are fabricated by using a promising photoresist technique. A proposed, self-aligned gate MOS FET structure (Grooved Gate MOS FET) is based on two-dimensional analyses of short channel devices. A characteristic feature of the device is negative source and drain junction depth. The fabricated 21 stage ring oscillator displays a high circuit performance for delay and power product of 0.12 pJ.

Approach for physical design in sub-100 nm era

In sub-100 nm processes, various physical phenomena come up as critical red-brick in designing circuits and LSIs. We focus on design for variability (DFV) for LSI-chip design, taking within-die variations into consideration. The main approach for the purpose is a new test structure, TEG (test element group), to measure the within-die variation of elements (MOS, R, C) and ring-oscillators. The precise measurement has been achieved with careful TEG design, including on-chip circuit, such as CBCM, Kelvin pattern. Reliable measurement data were analyzed statistically. Variation-caused systematic and random physical sources have been successfully decomposed with a newly developed extraction strategy. The data exhibits an extremely large variation in N/PMOS drain current (I/sub ds/) and threshold voltage (V/sub th/). The main sources of the random variation are doping fluctuation and line edge roughness (LER) in small size MOS transistors. I/sub ds/ variation is affected by the doping fluctuation. On the other hand, V/sub th/ variation is sensitive to LER. Interconnect variation is essentially small compared with the I/sub ds//V/sub th/ variation of MOS transistors; however, its variation is systematic component dominant. Ring oscillator T/sub pd/ variation is found to be closely related to I/sub ds/ variation, showing a correlation coefficient of 0.9. Design for variability is one of the most difficult challenges in 65-90 nm processes. Statistical design in the early stages will be necessary.

Development of a large-scale TEG for evaluation and analysis of yield and variation

We have developed the first TEG (Test Element Group) with large-scale patterns that compare well to those of an SoC; it also address decoders in its four corners. This TEG is based on the design rules of pure processes that are independent of the product. We have successfully measured pure process yield, failure terms, and failure locations. We evaluated characteristic chip variation, and performed stress tests. We verified the methodology for this TEG using five test chips with 100-nm physical gate lengths and five Cu interconnect layers that were fabricated using a 130-nm CMOS process. The developed TEG should become a strategic technology for measuring electrical dimension and charge-up damage and for analysis of database software.

A new defect distribution metrology with a consistent discrete exponential formula and its applications

We have proposed a novel discrete exponential distribution function, which describes a defect count distribution on wafers or chips more accurately, especially in near defect-free conditions. The conventional approach based on a gamma probability density function (g-pdf) is known to fail in expressing the defects of defect-free wafers or chips, because it always gives zero as the pdf value. Since the number of defects is countable (discrete distribution should be used) and analyzed in terms of nondefective chip yield, the g-pdf cannot be used because of its inaccuracy in the near defect-free condition. A discrete exponential pdf is introduced corresponding to the defect count distribution. In addition, a convolution formula of the new pdf is derived statistically which can express realistic defect count distribution with multiple defect sources. It is noted that the popular negative binomial yield formula (NBYF) is directly derived with the convoluted discrete exponential distribution, which interprets the cluster factor given in NBYF as the number of different defect sources predicted. It is experimentally proven that defect count distributions are approximated by this new model within an average error of about 0.01 defects per wafer from film deposition process data.

Accurate statistical process variation analysis for 0.25-/spl mu/m CMOS with advanced TCAD methodology

Effects of statistical process variation on the 0.25-/spl mu/m CMOS performance have been accurately characterized by using a new calibrated TCAD methodology. To conduct the variation analysis, a series of TCAD simulations was conducted on the basis of DoE (design of experiments) with optimum variable transformations, which resulted in RSFs (response surface functions) for threshold voltage (V/sub th/) and saturation drain current (I/sub ds/). A new global calibration of the RSF model based on experimental data gives excellent accuracy within 0.02 V error in V/sub th/ and 3% error in I/sub ds/. Using calibrated RSF, statistical process variation effects on the device characteristics have been quantitatively evaluated for each process recipe. It is found that variation of the gate-oxide formation process shows the most significant effect on the NMOS /spl Delta/I/sub ds/ in the production process. Furthermore we have designed an optimized 0.25-/spl mu/m CMOS process and device on the basis of the RSF and also predicted the process variation effects on the device performance. It is shown that the V/sub th/ and I/sub ds/ variations of the 0.25-/spl mu/m CMOS exhibit less than 10% I/sub ds/ variation in the production level process, which is similar to the value of 0.35-/spl mu/m CMOS experimental data. Additional TCAD simulations for MOS model parameter generation of the 0.25-/spl mu/m device was also conducted to allow circuit-designers to use predictive worst case circuit design parameters before experimental chip fabrication.

A new characterization of sub-/spl mu/m parallel multilevel interconnects and its experimental verification

This paper describes a new interconnect design and its verification with test-structures for sub-micron multilevel interconnection. A universal design-chart has been developed, which gives a precise sub-micron interconnect-capacitance for parallel multilevel interconnections. Test-structure measurements show excellent agreement with the design-chart within 4% error. A simple propagation delay model has also been developed.

Submicron Channel MOSFET Using Focused Boron Ion Beam Implantation into Silicon

A new submicron channel length device, ion beam MOSFET (IB-MOS), is proposed as an effective application of focused-ion-beam implantation into silicon. The effective channel region of this device is formed by the one line scan of a 16 keV, focused B+ ion beam (diameter: 0.2 µm, current density: 50 mA/cm2) in an As+ implanted n- gate region between the source and drain. It is demonstrated by two dimensional device simulation that significant improvements in current gain, drain breakdown voltage and short-channel threshold effect are achieved for IB-MOS devices with 0.8 µm source-drain spacing. A fabricated IB-MOS device verifies the results of the simulation, except for the current gain, because of the high impurity effect in the channel region, which could be improved by choosing appropriate channel implantation conditions.