Atsushi Kurokawa

Efficient capacitance extraction method for interconnects with dummy fills

The accuracy of parasitic extraction has become increasingly important for system-on-chip (SoC) designs. In this paper, we present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by the chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that the existence of the interlayer dummy metal fills has more significant influences than the intralayer dummies in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

With the scaling of complementary metal-oxide-semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

A gate delay model focusing on current fluctuation over wide-range of process and environmental variability

This paper proposes a gate delay model that is suitable for timing analysis considering wide-range process and environmental variability. The proposed model focuses on current variation and its impact on delay is considered by replacing output load. The proposed model is applicable for large variability with current model constructed by DC analysis whose cost is small. The proposed model can also be used both in statistical static timing analysis and in conventional corner-based static timing analysis. Experimental results in a 90nm technology show that the gate delays of inverter, NAND and NOR are accurately estimated under gate length, threshold voltage, supply voltage and temperature fluctuation. We also verify that the proposed model can cope with slow input transition and RC output load. We demonstrate applicability to multiple-stage path delay and flip-flop delay, and show an application of sensitivity calculation for statistical timing analysis

Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies

With the scaling of CMOS technology, the overshooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.

Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew

In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the Ceff of interconnect load for gate slew. We firstly establish a new expression for Ceff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of Ceff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of Ceff in 0.8Vdd point, Ceff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.

A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads

In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance Ceff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate Ceff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of Ceff. The introduction of Integration Approximation results in Ceff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.

A novel SRAM structure for leakage power suppression in 45nm technology

Due to aggressively scaling down the size of MOS transistor, leakage power dissipation becomes the key issue that is always concerned in SRAM design. In this paper, a novel structure named dynamic standby mode SRAM is proposed, which is based on the theory that both raising negative supply voltage, Vss, and reducing the difference between Vdd and Vss to its limit could cut down leakage current substantially. Furthermore, the impact of performance and the cost of additional area are also carefully considered. The simulation results based on a 45 nm technology model of BPTM (Berkeley predictive technology method) show that 55.8% and 80.2% leakage power is saved compared to DRV method and gated-Vdd SRAM, respectively (Qin et al., 2005 and Powell et al., 2000). Meanwhile, the stability of SRAM is guaranteed by choosing an appropriate value of Vss.

Impact of on-chip interconnects on vertical signal propagation in 3D ICs

Three-dimensional integrated circuits (3D ICs) provide a promising solution for overcoming delay/power problems of 2D ICs by stacking chips vertically. Signal propagation speed among the stacked chips is very important for 3D IC systems. We propose a simple model for analyzing the vertical signal propagation in through-silicon-via-based 3D ICs and discuss the impact of physical parameter variations on propagation delay. Experimental results show that on-chip interconnects greatly affect vertical signal propagation when there are dense general interconnects near the vertical signal interconnect, large amount of fanout, and interconnect length of a driver and receivers is long.

Calculating the Effective Capacitance for Interconnect Loads Based on Thevenin Model

Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance Ceff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to Ceff and RC-pi are not equal was not considered. With the progress of IC process technology, its influence on static timing analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation

Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay

The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.