Hiroomi Hikawa

Frequency-based multilayer neural network with on-chip learning and enhanced neuron characteristics

A new digital architecture of the frequency-based multilayer neural network (MNN) with on-chip learning is proposed. As the signal level is expressed by the frequency, the multiplier is replaced by a simple frequency converter, and the neuron unit uses the voting circuit as the nonlinear adder to improve the nonlinear characteristic. In addition, the pulse multiplier is employed to enhance the neuron characteristics. The backpropagation algorithm is modified for the on-chip learning. The proposed MNN architecture is implemented on field programmable gate arrays (FPGAs) and the various experiments are conducted to test the performance of the system. The experimental results show that the proposed neuron has a very good nonlinear function owing to the voting circuit. The learning behavior of the MNN with on-chip learning is also tested by experiments, which show that the proposed MNN has good learning and generalization capabilities. Simple and modular structure of the proposed MNN leads to a massive parallel and flexible network architecture, which is well suited for very large scale integration (VLSI) implementation.

A new digital pulse-mode neuron with adjustable activation function

This paper describes a new pulse-mode digital neuron which is based on voting neuron. The signal level of the neuron is represented by frequency of pulse signals. The proposed neuron provides adjustable nonlinear function, which resembles the sigmoid function. The proposed neuron and experimental multilayer neural network (MNN) are implemented on field programmable gate array (FPGA) and various experiments are conducted to test the performance of the proposed system. The experimental results show that the proposed neuron has rigid adjustable nonlinear function.

A radix-8 wafer scale FFT processor

Wafer Scale Integration promises radical improvements in the performance of digital signal processing systems. This paper describes the design of a radix-8 systolic (pipeline) fast Fourier transform processor for implementation with wafer scale integration. By the use of the radix-8 FFT butterfly wafer that is currently under development, continuous data rates of 160 MSPS are anticipated for FFTs of up to 4096 points with 16-bit fixed point data.

2005 Special issue: FPGA implementation of self organizing map with digital phase locked loops

The self-organizing map (SOM) has found applicability in a wide range of application areas. Recently new SOM hardware with phase modulated pulse signal and digital phase-locked loops (DPLLs) has been proposed (Hikawa, 2005). The system uses the DPLL as a computing element since the operation of the DPLL is very similar to that of SOMs computation. The system also uses square waveform phase to hold the value of the each input vector element. This paper discuss the hardware implementation of the DPLL SOM architecture. For effective hardware implementation, some components are redesigned to reduce the circuit size. The proposed SOM architecture is described in VHDL and implemented on field programmable gate array (FPGA). Its feasibility is verified by experiments. Results show that the proposed SOM implemented on the FPGA has a good quantization capability, and its circuit size very small.

On simultaneous perturbation particle swarm optimization

In this paper, we describes the simultaneous perturbation particle swarm optimization which is a combination of the particle swarm optimization and the simultaneous perturbation optimization method. The method has global search capability of the particle swarm optimization and local search one of gradient method by the simultaneous perturbation. Some variations of the method are described. Comparison between these methods and the ordinary particle swarm optimization are shown through five test functions and learning problem of neural networks.

Novel FPGA Implementation of Hand Sign Recognition System With SOM–Hebb Classifier

This paper proposes a hardware posture recognition system with a hybrid network. The hybrid network consists of self-organizing map (SOM) and Hebbian network. Feature vectors are extracted from input posture images, which are mapped to a lower dimensional map of neurons in the SOM. The Hebbian network is a single-layer feedforward neural network trained with a Hebbian learning algorithm to identify categories. The recognition algorithm is robust to the change in location of hand signs, but it is not immune to rotation or scaling. Its robustness to rotation and scaling was improved by adding perturbation to the training data for the SOM-Hebb classifier. In addition, neuron culling is proposed to improve performance. The whole system is implemented on a field-programmable gate array employing novel video processing architecture. The system was designed to recognize 24 American sign language hand signs, and its feasibility was verified through both simulations and experiments. The experimental results revealed that the system could accomplish recognition at a speed of 60 frames/s, while achieving an accuracy of 97.1%. Due to a novel hardware implementation, the circuit size of the proposed system is very small, which is highly suitable for embedded applications.

Implementation of simplified multilayer neural networks with on-chip learning

In this paper, a new digital architecture of multilayer neural network (MNN) with on-chip learning is proposed. Proposed MNN is designed to have no multiply operation for efficient hardware implementation. The absence of the multiplier makes the circuit size small, thus the proposed MNN is suitable for massively parallel VLSI implementation. To provide the on-chip learning ability, the back-propagation algorithm is modified to have no multiply operation, and the algorithm is implemented with pulse-mode operation. Further, a tri-state function is used as the activate function of neurons so that the multipliers in forward path is replaced by a combination of shift and logical AND operations, which are easily realized by digital circuits. The proposed MNN is implemented on a field programmable gate array (FPGA) and tested. To verify the feasibility of the proposed MNN in the larger application, the MNN design is tested using a pattern recognition problem by computer simulations.

An architecture for WSI rapid prototyping

Wafer-scale integration architecture for rapid prototyping (WARP), a generalized architecture for rapid prototyping, is discussed. The primary goal of rapid prototyping is to map one of several members of a class of algorithms using a single-wafer architecture. The wafer can be personalized for the algorithm by either soft or hard-restructuring. The WARP wafer consists of an array of two types of cells specifically defined for this architecture: the universal multiply-subtract-add (UMSA) cell and the universal nonlinear (UNL) cell. Reconfiguration of the algorithms in the presence of defects, a harvesting probability model and yield, and wafer-scale testing and test facilities are described.<<ETX>>

Hardware friendly vector quantization algorithm

This paper proposes a new vector quantization algorithm that can be directly implemented by hardware and its performance is discussed. The algorithm is based on the assumption that most of the vector elements in the same class fall within a certain range. The proposed algorithm provides very fast vector quantization with a dedicated hardware. VHDL simulations with real world data verify the feasibility of the system followed by the circuit size and speed evaluation. Results show that the proposed system has higher performance than those of K-nearest-neighbor method or neural network approach.

Defect tolerance and yield for a wafer scale FFT processor system

A wafer scale system for frame-by-frame computation of the fast Fourier-transform (FFT) is described. It is based on an eight-point FFT wafer design, which uses two types of cells, a multiply-subtract-add (MSA) cell and a coefficient ROM cell. Systematic repetition of these cells and the interconnect forms the physical wafer. The cells are designed for high performance and testability. For successive 512-point frames, the throughput is estimated at 20 million samples/s. Innovations in preplacement have reduced the traffic in the interconnect channels while enhancing the reconfigurability in the presence of defects. Estimates of wafer yield using a new model for harvesting probability are also presented.<<ETX>>