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Dive into the research topics where Hiroshi Hamano is active.

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Featured researches published by Hiroshi Hamano.


Journal of Lightwave Technology | 1994

Packaging technology for a 10-Gb/s photoreceiver module

Y. Oikawa; Haruhiko Kuwatsuka; T. Yamamoto; Takeshi Ihara; Hiroshi Hamano; T. Minami

We designed a 10-Gb/s photoreceiver module integrating a flip-chip avalanche photodiode (APD), a Si-preamplifier IC, and a slant-ended fiber (SEF). Flip-chip bonding minimizes parasitic reactances in the interconnect between the photodiode and the preamplifier IC. The optical coupling system consists of a slant-ended fiber and a microlens monolithically fabricated on the photodiode. This gives a flat IC-package assembly, which enables stripline interfaces to extract high-speed signals, increases misalignment tolerances, and lowers package height. Tolerances of over /spl plusmn/9 /spl mu/m were obtained in every direction, which matched our theoretical predictions. To attach and hermetically seal the optical coupling, the fiber ferrule was directly laser-welded to the package wall with a double ring structure. The module withstood shock and vibration tests and had a 10-GHz bandwidth and /spl minus/23-dBm minimum photosensitivity at 10 Gb/s. >


IEEE Journal on Selected Areas in Communications | 1991

High-speed Si-bipolar IC design for multi-Gb/s optical receivers

Hiroshi Hamano; T. Yamamoto; Y. Nishizawa; A. Tahara; H. Miyoshi; K. Suzuki; A. Nishimura

The authors developed several special circuits to minimize the decrease in speed caused by parasitics. The common-base circuit assures flat and wide frequency preamplifier response even when V/sub ee/ is unstable because of bond wire inductance. Cascode interconnections between circuit blocks prevent waveform degradation due to line capacitance discharge. The high level of integration prevents the signal speed from decreasing due to chip interfaces and external interference. Using these circuits and Si-bipolar ESPER (emitter-base self-aligned structure with polysilicon electrodes and resistors) transistors whose f/sub T/ was 28 GHz, the authors fabricated three ICs: a preamplifier with a 5.1 GHz bandwidth, a fully integrated automatic gain control (AGC) amplifier with a 3.6 GHz bandwidth, and a decision circuit that operates at 10.6 Gb/s. The authors used these ICs and an avalanche photodiode (APD) to construct a 5 Gb/s optical receiver with a minimum detectable optical power of -26.8 dBm. The speed of the Si ICs exceeded 5 Gb/s. >


15th Annual GaAs IC Symposium | 1993

AlGaAs/GaAs HBTs with high f/sub max/ for high-speed optical modulator driver circuit

K. Sakita; H. Endo; K. Ishii; H. Ohnishi; K. Yamashita; T. Ihara; Hiroshi Hamano; T. Fujii; N. Yokoyama

AlGaAs/GaAs HBTs having an f/sub max/ of 120.9 GHz and a breakdown voltage over 10 V of BV/sub ceo/ suitable for a high-speed and large voltage swing driver circuit have been demonstrated. Using these HBTs, an optical external modulator driver circuit with 29 ps of t/sub /spl tau// and 25 ps of t/sub f/ which make it possible to operate at 10 Gb/s was realized.<<ETX>>


Electronics Letters | 1991

10 Gbit/s optical front end using Si-bipolar preamplifier IC, flipchip APD, and slant-end fibre

Hiroshi Hamano; T. Yamamoto; Y. Nishizawa; Y. Oikawa; H. Kuwatsuka; A. Tahara; K. Suzuki; A. Nishimura


Archive | 1992

Method of producing an electronic circuit package

Yasunari Arai; Hiroshi Hamano; Izumi Amemiya; Takuji Yamamoto; Takeshi Ihara


Archive | 1998

Equalizing filter and control method for signal equalization

Takeshi Ihara; Hiroshi Hamano


Archive | 1993

Filter circuit and filter integrated circuit

Hiroshi Hamano; Izumi Amemiya; Yoichi Oikawa; Takuji Yamamoto; Takeshi Ihara; Yoshinori Nishizawa


Archive | 1988

High-speed electronic circuit having a cascode configuration

Hiroshi Hamano; Izumi Amemiya; Takuji Yamamoto; Hiroo Kitasagami; Takeshi Ihara


Archive | 1991

Data delay circuit and clock extraction circuit using the same

Hiroshi Hamano; Izumi Amemiya; Takuji Yamamoto; Yasunari Arai; Takeshi Ihara


Electronics Letters | 1991

20 Gbit/s AlGaAs/GaAs-HBT 2:1 selector and decision ICs

Hiroshi Hamano; Takeshi Ihara; I. Amemiya; T. Futatsugi; K. Ishii; H. Endoh

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