Hiroshi Tomonaga

High-speed switching module for a large capacity ATM switching system

An ultra-high-speed asynchronous transfer mode (ATM) switching module having a highway throughput of 9.6 Gb/s using a HEMT process switch IC and a ceramic multichip substrate was developed. The switch IC operates at 1.2 Gb/s. This module provides a 4*4 switch, corresponding to a switching capacity of 256 channels at 156 Mb/s. High-speed switching is essential for constructing a large switching system with small volume and low power consumption. A simulation of both cell buffer operation and line characteristic is presented. The experimental results are shown.<<ETX>>

Application and evaluation of distributed WAN optimization technique in heterogeneous networks

WAN optimization becomes a well-known technique to improve transmission rate in file transfer applications and interactive applications served in international cloud services. WAN optimization technique can improve transmission speed by using high performance protocols instead of TCP between both ends of wide area network, which has a large round trip time and a high packet loss rate. There are some kinds of high performance protocols, and their effectiveness in improving communication are different from each other based on the characteristics of the networks and applications. When WAN optimization technique is only used at both ends of a heterogeneous network containing networks such as wireless networks, international leased lines, etc. (e.g., access from a mobile device to a foreign cloud data center), improvement in communication is limited because only one high performance protocol is being applied. Therefore, we propose “distributed WAN optimization technique” that dynamically changes high performance protocols and sections to adapt those protocols based on network characteristics and applications.

Proposal for ultra-high speed scheduling architecture

It has recently become more difficult for packet processing switches, which have very high speed interface cards, to achieve rich Quality of Service (QoS) functions because such high-speed switches have insufficient packet processing times. In particular, the scheduler/shaper is one of the greatest hindrances to increasing the speed of processing because it selects a suitable queue based on complex algorithms (e.g., weighted round robin (WRR) or strict priority (SP)) in a limited time. One solution that mitigates this scheduling/shaping speed problem is burst packet processing. However, burst packet processing has several side effects. We analyze these side effects and propose a scheduling architecture that minimizes them. We also show the effectiveness of our proposed architecture based on simulation results.