Kenichi Okabe

Extension Engineering using Carbon co-Implantation Technology for Low Power CMOS Design with Phosphorus- and Boron-Extension

We have developed a carbon (C) co-implantation technology that enables drastic improvement of Vth rolloff in nMOSFET having phosphorus (P) extension while maintaining the current drive, and reduces the extension sheet resistance in pMOSFET having boron (B) extension. The data revealed that C introduced into the extension region suppresses the P-extension tail for nMOSFET and improves B activation ratio for pMOSFET. We also found that combination of C and indium (In) pocket plays an important role for Vth rolloff improvement in nMOSFET.

65nm Device Characteristics Matching on Single and Batch System Ion Implanter

We examined the process matching between two types of high current implanters; a batch system and a single wafer system. In particular, we investigated the formation by ion implantation of ultra shallow junctions for device characteristics of 65nm generation CMOS logic transistors. Secondary ions mass spectroscopy (SIMS) measurements were performed to profile boron and arsenic. Sample were implanted under various conditions by both types of implanters. The device characteristics were successfully matched using the adjusted implanted conditions using the SIMS profile.

Suppression of gate depletion in p+-polysilicon-gated sub-40 nm pMOSFETs by laser thermal processing

Laser thermal processing (LTP) was investigated as a gate pre-annealing technique and its advantages over rapid thermal annealing (RTA) with regard to both gate activation and suppression of boron penetration were confirmed by evaluating the electrical characteristics of sub-40 nm p-metal oxide semiconductor field effect transistors (pMOSFETs). Laser annealing transformed amorphous Si in which high doses of boron were implanted into poly-Si with highly activated boron profiles down to the gate/gate oxide interface. By suppressing gate depletion with suppressing boron penetration, LTP results in an on-current at Ioff=70 [nA/µm] that is 4% greater than that in a device fabricated using conventional RTA. The off-state Ig current that flows mainly from the p+ poly-Si gate to the drain overlap region is smaller in devices fabricated using LTP because the reduced roughness of the poly-Si gate/gate oxide interface in these devices reduces the local electric field enhancement.

Suppression of Gate Depletion in p+ Polysilicon Gated Sub-40nm PMOS Devices by Laser Thermal Process

Introduction For aggressively scaling of CMOS devices, thinner gate oxide is required, and at the same time, suppression of gate depletion is also important. Low thermal budget source-drain rapid thermal annealing (SD-RTA) processing becomes more important to maintain shallow junctions for well-controlled short channel effects. However, low thermal budget SD-RTA tends to induce severe poly-Si gate depletion due to low dopant diffusivity and activation and, as a result, device performance is degraded. Thus, gate pre-doping and pre-annealing technique becomes more important to control thermal budget for SD annealing independently [1,2]. Fig. 1 shows the electrical inversion oxide thickness and threshold voltage (Vth) shift as a function of gate annealing conditions for p+ poly-Si gated PMOSFET as an example. By applying gate pre-annealing, gate depletion is clearly suppressed and higher annealing temperature is more effective due to higher dopant diffusion and activation. However, at the same time, high temperature annealing tend to induce the positive shift of Vth due to boron penetration through the gate oxide and into the channel region. In our experiments, 0.01nm improvement requires 80mV of Vth shift (see low to high temperature). This implies that suppression of gate depletion and boron penetration, which causes performance degradation, Vth variation and reliability issues tend to fall into the relations of the trade-off. Recently, gate activation by laser thermal process (LTP) has been reported [3], and its characteristics of sub-40nm MOSFETs have also been reported [4,5]. In this paper, we report, for the first time, that LTP as a gate pre-annealing is superior to RTA for both gate activation and suppression of boron penetration.

A novel polysilicon gate engineering by laser thermal process for high performance sub-40 nm CMOS devices

A novel polysilicon gate engineering by laser thermal process (LPT) is developed to minimize the gate depletion even under low temperature SD-RTA and applied to sub-40 nm CMOS devices. BEOL process is optimized to suppress dopant deactivation. SD-RTA technique is developed to supress dopant dose loss for the maximization of the merit of LTP.