Hirotaka Maruyama

Computational image sensor for on sensor compression

We propose a novel integration of image compression and sensing in order to enhance the performance of an image sensor. By integrating a compression function onto the sensor focal plane, the image signal to be read out from the sensor is significantly reduced and the pixel rate of the sensor ran consequently be increased. The potential applications of the proposed sensor are in high pixel-rate imaging, such as high frame-rate image sensing and high-resolution image sensing. The compression scheme we employ is a conditional replenishment, which detects and encodes moving areas. In this paper, we introduce two architectures for on-sensor compression; one is the pixel parallel approach and the other is the column parallel approach. We prototyped a VLSI chip of the proposed sensor based on the pixel parallel architecture. We show the design and describe the results of the experiments obtained by the prototype chip.

A CMOS imager hybridized to an avalanche multiplied film

A highly sensitive solid-state imager has been made by connecting an avalanche multiplier film to a MOS readout circuit through microbump electrodes. Optimization of the vapor-deposition conditions for the indium bump material made it possible for microbumps 5 /spl mu/m in diameter and 5 /spl mu/m in height to be formed into a 2/3-in matrix array of 380 000 pixels. A prototype imager was constructed with a 0.5-/spl mu/m thick avalanche photoconductive film. Clear avalanche multiplication of about ten times was observed at an applied voltage of 75 V. The imager had a good resolution and no recognizable afterimages.

Computational image sensors for on-sensor-compression

In this paper, we propose novel image sensors which compress image signal. By making use of very fast analog processing on the imager plane, the compression sensor can significantly reduce the amount of pixel data output from the sensor. The proposed sensor is intended to overcome the communication bottle neck for high pixel rate imaging such as high frame rate imaging and high resolution imaging. The compression sensor consists of three parts; transducer, memory and processor. Two architectures for on-sensor-compression are discussed in this paper that are pixel parallel architecture and column parallel architecture. In the former architecture, the three parts are put together in each pixel, and processing is pixel parallel. In the latter architecture, transducer, processor and memory areas are separated, and processing is column parallel. We also describe a prototype chip of pixel-parallel-type sensor with 32/spl times/32 pixels which has been fabricated using 2 /spl mu/m CMOS technology. Some results of examinations are shown in this paper.

On sensor image compression based on pixel parallel and column parallel architectures

We propose a novel concept of an integration of compression and sensing in order to enhance performance of the image sensor. By integrating compression function on the sensor plane, the image signal that has to be readout from the sensor is significantly reduced. Thus, the integration can consequently increase the pixel rate of the sensor. The compression scheme we make use of is conditional replenishment that detects and encodes moving areas. In this paper, we discuss design and implementation of two architectures for on sensor compression. One is pixel parallel approach and the other is column parallel approach. We describe and compare both approaches.

Solid State Imaging Techniques. A Novel Image Sensor for On-Sensor-Compression.

In this paper, we propose a novel image sensor by which the image signal can be compressed. Since the image signal is compressed on the imager plane by making use of the parallel nature of image signals, the amount of signal readout from the imager can be significantly reduced. Thus, the proposed sensor can potentially be applied to high-pixel-rate cameras and real-time processing systems which require very high-speed imaging and very high resolution for real-time imaging; the very high bandwidth is the fundamental limitation to the feasibility of such high-pixel-rate sensors and processing systems. The proposed sensor utilizes a conditional replenishment algorithm; it detects temporally changing pixels as active pixels and output them. An analog circuit for processing in each pixel and an entire sensor architecture have been designed. A first prototype of a VLSI sensor chip has been fabricated. Results of experiments using the prototype chip are shown.

Sensor image compression for very high pixel-rate imaging and processing

In this paper, we propose a novel image sensor which compresses image signal on the sensor plane. Since image signal is compressed on the sensor plane by making use of the parallel nature of image signals, the amount of signal read out from the sensor can be significantly reduced. Thus, the proposed sensor can be potentially applied to high pixel rate cameras and processing systems which require very high speed imaging or very high resolution real time imaging. The very high bandwidth is the fundamental limitation to the feasibility of those high pixel rate sensors and processing systems. Conditional replenishment is employed for the compression algorithm. In each pixel, current pixel value is compared to that in the last replenished frame. The value and the address of the pixel is extracted and coded if the magnitude of the difference is greater than a threshold. Analog circuits have been designed both for processing in each pixel and for controlling entire data rate. A first prototype of a VLSI chip has been fabricated. Some results of experiments obtained by using the first prototype are shown in this paper.

Focal plane compression sensors

We propose a novel integration of compression and sensing in order to enhance performance of the image sensor. By integrating compression function on the sensor plane, the image signal that has to be readout from the sensor is significantly reduced. Thus, the integration can consequently increase the pixel rate of the sensor. The compression scheme we make use of is conditional replenishment that detects and encodes moving areas. In this paper, we discuss design and implementation of two architectures for on sensor compression. One is pixel parallel approach and the other is column parallel approach. We describe and compare both approaches.

Characteristics of a new high-sensitivity X-ray imaging tube for video topography

A new type of high-sensitivity X-ray imaging tube having an amorphous selenium photoconductive layer with a thickness of 8 µm has been fabricated. Signal charges induced by X-ray photons can be avalanche-multiplied in the photoconductive layer under a large electric field. The sensitivity of the tube reaches the level of individual X-ray photon detection. For the detection of such a small number of X-ray photons, a new kind of noise is generated due to the fluctuation of absorption depth in the photoconductive layer under the operation conditions of avalanche multiplication. Signal-to-noise ratio can be improved by the accumulation of signal charges in the photocon-ductive layer. An example of real-time X-ray topography by weak X-rays using this experimental tube is demonstrated.