Hiroyoshi Komobuchi

A 2.2/3-inch 4K2K CMOS image sensor based on dual resolution and exposure technique

The recent trend in ultra-high-density cameras is running from HD to 4K2K, which will further extend to 8K4K / portable 4K2K. With advancements in device fabrication process technologies, there has been a pressing need for the miniaturization as well as high resolution and high sensitivity in image sensors [1].

High-speed high-resolution epifluorescence imaging system using CCD sensor and digital storage for neurobiological research

We have designed and built a high-speed CCD imaging system for monitoring neural activity in an exposed animal cortex stained with a voltage-sensitive dye. Two types of custom-made CCD sensors were developed for this system. The type I chip has a resolution of 2664 (H) X 1200 (V) pixels and a wide imaging area of 28.1 X 13.8 mm, while the type II chip has 1776 X 1626 pixels and an active imaging area of 20.4 X 18.7 mm. The CCD arrays were constructed with multiple output amplifiers in order to accelerate the readout rate. The two chips were divided into either 24 (I) or 16 (II) distinct areas that were driven in parallel. The parallel CCD outputs were digitized by 12-bit A/D converters and then stored in the frame memory. The frame memory was constructed with synchronous DRAM modules, which provided a capacity of 128 MB per channel. On-chip and on-memory binning methods were incorporated into the system, e.g., this enabled us to capture 444 X 200 pixel-images for periods of 36 seconds at a rate of 500 frames/second. This system was successfully used to visualize neural activity in the cortices of rats, guinea pigs, and monkeys.

8-channel parallel readout high-speed wide dynamic range CCD

An 8 channel parallel readout CCD image sensor for high-speed imaging has been developed. The image area of this sensor is divided into 8 rectangular blocks, and the data of each block is read out through an independent amplifier. In the area where there is not photediode (PD) beside VCCD, the space of VCCDs is narrowed down to a HCCD block that is placed at the end of VCCDs, and amplifiers and their peripheral circuits are placed between the spaces of two HCCD blocks with parallel to makes amplifier properties uniform across channels. For VCCD high-speed transfer, VCCD bus line structure is used and VCCD slant structure is optimized by the computer 3D simulation. The pixel size is designed to be 11.5 micrometers X 11.5 micrometers , and amplifiers are placed close to FDA (Floating Diffusion Amplifier) with VCCD slant structure, which realized high sensitivity and large saturation.

An edge breakdown free MOS-avalanche photodiode image sensor cell

An edge-breakdown-free MOS avalanche photodiode (APD) cell without avalanche multiplication during the readout period was proposed and simulated for a 5 mu m*5 mu m photosite. From the simulation results, the MOS-APD cell showed three times the sensitivity of the conventional photosite under a 20 V driving voltage. >