Hiroyuki Fukai

New fine line fabrication technology on glass-cloth prepreg without insulating films for PKG substrate

As electronic parts increase its performance and miniaturize in its size, package substrates are demanded to be thinner and higher in density. But higher density substrates using insulating films give higher warpage values when they are very thin, due to its low modulus. Packages with glass-cloth prepreg as its outer-layer have lower warpage, but making a 40 μm pitch package with them are difficult because it cannot adapt to the semi-additive method. Conventional insulating films can be applied to the semi-additive method; however, a process of roughing the surface of the insulating films by chemicals is required, causing the limitation of material of insulating films. Therefore, we developed a new technology of semi-additive primer (SAPP) with glass-cloth prepregs which allows higher density and lower warpage for substrates. Under 30 μm pitch wiring of SAPP applied substrates were easier compared to conventional substrates made from the insulating film semi-additive method. Also, the roughening process (Ra=0.50–0.60 μm) of conventional insulating films to achieve adhesion strength with plated copper makes high density wiring difficult. But the new SAPP system has a surface roughness of Ra <0.25 μm with high adhesive strength which allows easy high density wiring. It has been made clear that by providing a new adhesive-agent layer, peel strength equivalent to that of the roughened insulating film (0.7 kN/m or more) can be obtained with sufficient reliability. The thinner package boards consisting of our new low-CTE and high modulus insulation prepreg E-700G(R) and SAPP have lower warpage than that of build-up structure and coreless structure using conventional insulating films. The package substrates made of SAPP with E-700G(R) core show low coefficient of thermal expansion (9–10 ppm/°C) and high modulus of tensile elasticity (32 GPa), with 20 μm pitch wiring possible.

High performance photo-sensitive insulating materials for high density multi-layer wiring boards

The photo-via build-up process is a most significant candidate for fabrication of high density multi-layer wiring boards for high density packaging using CSP and flip-chip direct attach. We have developed a new type of photo-sensitive dielectric. The dielectric delivers high resolution in fabrication of photoformed microvia holes with an aspect ratio of 1.0. The photo-sensitive dielectric showed excellent electrical and mechanical properties for surface mounted wiring boards. It also shows outstanding mechanical properties, especially in the high temperature region. Excellent insulating properties and adhesion were proven, even after pressure cooker test (PCT) conditions. These features offer a great advantage in achieving higher interconnect reliability in direct-chip attachment on low cost multichip modules using sequential build-up substrates.

High performance photo-sensitive insulating materials for MCM-L

The sequential build-up process with photo-sensitive dielectric is a most significant candidate for achieving high density multilayer wiring substrates for low cost multichip modules. A high performance dielectric material is essential in order to obtain high reliability on the wiring substrate. Two types of photo-imageable dielectric have been developed: an aqueous alkaline developable type and a semi-aqueous developable type. The results of the performance evaluation of the dielectric materials and sequential build-up wiring substrates are described here. Both dielectric types deliver high resolution in fabricating photo-formed micro-via holes. The maximum aspect ratio of the micro-via has reached 1.0 for both materials. The aqueous developable type photodielectric showed excellent electrical and mechanical properties for surface mount wiring boards with a panel electroplate subtractive process. The semi-aqueous type high performance photo-dielectric, designed for MCM-L, showed outstanding mechanical properties especially in a high temperature region. Excellent insulating properties and adhesion were proven even after pressure cooker test (PCT) conditions. Sufficient adhesion for full-build electroless copper metallization was also achieved. These features offer a great advantage in achieving higher interconnect reliability in direct chip attachment on low cost multichip modules using sequential build-up substrates.