Hiroyuki Tsukahara

Automated visual inspection system for bonded IC wires

Abstract This paper discusses an automated visual inspection system for bonded IC wires. The system uses high-contrast image capture, an algorithm for accurately measuring the bonding balls, and a wire inspection algorithm. The high contrast image capture system consists of a wide-area camera and two types of lighting optics, one for ball sensing and the other for wire sensing. The algorithm for measuring the bonding balls is based on morphological techniques, and the wire inspection algorithm is based on a border following algorithm. The automated inspection system measures ball diameters to with in ± μ m accuracy, which corresponds to half a pixel of the captured picture. The system takes 0·2 s to inspect a wire and ball. Combining the inspection system with an automatic wire bonder enables a fully automatic bonding system to be constructed.

High-speed solder bump inspection system using a laser scanner and CCD camera

We have developed technologies which inspect the shape of solder bumps. The bumps are used to solder an LSI to a printed wiring board in high-speed workstations. The inspection system developed can measure the height, diameter, and brightness of bumps at very high speed. The bump height is measured using triangulation, in which a laser beam scans the bumps, and reflected light is detected with a position sensitive detector (PSD). The diameter and the brightness are measured using a microscope and a CCD camera. The detected results are compared with CAD data. A height measurement accuracy of ±3 μm and a diameter measurement accuracy of ±5 μm were obtained. Practical inspection systems using these techniques have been created and they can inspect 2000 bumps in 60 seconds.

Automated visual inspection system for IC bonding wires using morphological processing

This paper discusses an automated visual inspection system for IC bonding wires that uses high-contrast image capture and an accurate bonding-ball measurement algorithm. On IC assembly lines visual inspection is vital to maintaining IC reliability. Wire bonding requires the automated evaluation of bonding quality to maintain productivity. Both bonding balls and wires must be inspected to evaluate bonding quality. We developed a bonding-ball measurement algorithm based on subpixel and morphological techniques and a wire inspection algorithm based on border following. The automated inspection system measures ball diameters to an accuracy within jim which corresponds to one-half pixel taking 0. 2 seconds to inspect a wire and ball. Paired with a wire bonder the inspection system configures a fully automatic bonding system.

Development of high-speed 3D inspection system for solder bumps

We developed a high-speed 3D inspection system for solder bumps. The system applies laser-based triangulation with a laser diode, an acousto-optical deflector (AOD), and a position sensitive detector. The system scans LSI surfaces with a laser beam at a 15 m/s scanning speed, and can acquire height data at rate of up to 7 X 106 samples/sec with 0.8 micrometers resolution. For high-speed laser beam scanning with the AOD, we developed a technique to correct for the cylindrical lensing effect that causes astigmatism on a focal plane. Our correction method is unique in that it notices the scanning speed being constant in order for the dynamic deviation to be erased. This technique can suppress these deviations enough to enable accurate laser scanning. When installed on an LSI chip assembly line, the system can measure each bump height to within +/- 2 micrometers in 5 ms. This will allow for a 100% inspection to be achieved.

High-speed 3D inspection system for solder bumps

This paper discusses a high-speed 3-D inspection system for solder-bumps. The system uses a high-speed 3-D sensor system and an accurate measurement algorithm. Solder-bumps have recently been used for flip-chip bonding. Before bonding all bumps need their height and diameter inspected and if bumps are too big or too small, there is a danger of short or open circuits occurring after bonding on the substrate electrodes. Thus, a 100% inspection is required to assure high flip-chip bonding process yields. We developed a laser-based high- speed bump height capture system and an accurate bump height and diameter measurement algorithm. The inspection system takes 20 milliseconds to measure the height and diameter of a bump. It measures the bump height to an accuracy of plus or minus 3 micrometer, and the bump diameter to plus or minus 5 micrometer. Thus, this system is suitable for performing a 100% inspection of solder-bumps.

Observation of nanometer-scale crystal grain orientation in ferroelectric thin films using polarization near-field scanning optical microscopy (NSOM)

We developed an observation technique for crystal orientation in the nanometer-scale grain using polarization near-field scanning optical microscopy (NSOM), and applied it to Pb(Zr,Ti)O3 (PZT) ferroelectric thin films. PZT is a ferroelectric RAM material. Because ferroelectric RAM cell sizes have become smaller and are now, being measured in the submicron scale range, the grain sizes in PZT that constitute the cells are about 100 nm. The observation for crystal grain orientation of such ferroelectric RAM cells has been difficult with current methods such as X-ray diffraction method or micro-Raman spectroscopy. PZT is a uniaxial crystal because of its tetragonal structure and we found that the birefringence retardation of PZT depends on its crystal grain orientation. The nanometer-scale grain was observed by NSOM, which is not limited by the diffraction limit of conventional optical microscopy. To achieve the observation of birefringence retardation, NSOM and polarization optical elements were integrated. For this integration, the optical compensation of polarized light was indispensable because a near-field probe in NSOM might show birefringence. Then, a polarization compensation method at the tip of the near-field probe was developed. Using this polarization NSOM, a new technique for observing the crystal grain orientation by birefringence retardation was developed.

Automatic Visual Inspection System For IC Bonding Wires

This paper discusses a high-contrast imaging capture system and a wire inspection algorithm for an automatic visual inspection system. On IC assembly lines, automated visual inspection is essential to maintain IC productivity and reliability. An automatic inspection system requires realtime inspection without defects overlooked. To overcome the difficulties of getting clear wire images and inspecting flexible object shapes, we developed a high-contrast imaging capture system and a wire inspection algorithm. The imaging capture system consists of a special camera, called a MegaCamera, by Fujitsu Ltd. , and structured lighting. The MegaCamera satisfied both the requirements of 10-micron-per-pixel inspection resolution and an image capture area of 20 mm square. The structured lighting optic enabled us to get bright wire images and to reduce background noise. The wire inspection algorithm is based on border following. The algorithm enabled us to inspect curved and straight wires and to detect defects including broken wires, too close wires, and incorrect wiring paths. When we installed the system on an actual IC assembly line, it took 28 s to inspect a 68-wire IC. The rate of correct detection is 99.7 percent for ICs and the rate of overlooked defects is 0 percent. These results indicate the system can inspect in real time without defects overlooked, which up to now have required visual inspection.

Pattern recognition techniques for hybrid microcircuits

The paper discusses pattern recognition techniques for automatic hybrid IC assembling systems. The problems concerning recognition systems are flexibility and high recognition rates for various object patterns comprised of hybrid ICs. To overcome these problems we developed two new recognition algorithms based on pattern matching methods. One method recognizes speckle pattern (printed thick-film conductor patterns) locations using matrix filtering. The other method increases the matching SNR to 4.5 times greater than previous methods using peak sharpening of the matching degree curve. These algorithms enable recognition of more than 99% (99.8% on average) of all semiconductor chip patterns (ICs, transistors, and diodes) and printed thick-film conductor patterns.