Hiroyuki Utsumi

Bus control system for integrated circuit device with improved bus access efficiency

Data processor having instruction cache with low power consumption

Reset control system and method

Data processing system for performing software intialization

Cache system and shared secondary cache with flags to indicate masters

Processor and reset control method for the processor

Method and processor for initializing a plurality of non-overlapping areas with associated flags and signals

Processor with instruction cache with low power consumption

Prozessor mit Befehlscache mit niedrigem Stromverbrauch Processor with instruction cache with low power consumption

Prozessor und Verfahren zum Steuern der Rückstellungssequenz des Prozessors Processor and method for controlling the resetting sequence of processor