Hideyuki Iino

Clock circuit having a clocked output buffer

Data processing system, memory access device and method including selecting the number of pipeline stages based on pipeline conditions

Direct memory access controller with expedited error control

Processor system including an index buffer circuit and a translation look-aside buffer control circuit for processor-to-processor interfacing

Semiconductor integrated circuit having a DC test function

Reset control system and method

Arithmetic operation unit and memory accessing device for accessing primary and secondary cache memories independently of a CPU

Data processing apparatus for executing a vector operation under control of a master processor

Pipelined data processing device having improved hardware control over an arithmetic operations unit

Multiple bank structured memory access device having flexible setting of a pipeline stage number