Hiroyuki Yoshimoto

Local

The silicon on thin buried oxide (SOTB) has the smallest V th variation among planar CMOS due to a low-dose channel. This study focuses on evaluating local variability components and searching for the dominant factor after reducing random-dopant fluctuation (RDF) by decreasing impurities in the channel. Improving short-channel-effect immunity is important to reduce both the global and local variations. The local V th variation A Vt was very small, ~ 1.0 and 0.7 mV·¿m for NMOS and PMOS, respectively; however, additional unknown factors other than RDF still exist. Silicon-on-insulator thickness variation does not play a major role in ¿V th , and the SOTB is scalable to less than 25 nm while maintaining small variability and, hence, low power consumption. The larger variability in NMOS compared to that in PMOS cannot be explained by conventional RDF but seems to be strongly related to channel doping.

V_{\rm th}

The Silicon on Thin BOX (SOTB) has the smallest Vth variation among planar CMOS due to low-dose channel. This study focused on identifying the remaining components after reducing random-dopant fluctuation (RDF) by decreasing impurities in the channel. Improving short-channel-effect immunity and body-thickness uniformity is the key to further reducing the variation. An often mentioned phenomenon, larger variability in NMOS than PMOS, cannot be explained by conventional RDF but is surely related to channel doping.

Variability and Scalability in Silicon-on-Thin-BOX (SOTB) CMOS With Small Random-Dopant Fluctuation

Evidence is given for the mechanism of hole-trap-related random telegraph noise (RTN) in reverse-biased junction leakage current occurring in the off-state of sub-micron scaled metal-oxide-semiconductor field-effect transistor (MOSFET). It was found that such RTN in junction leakage current, namely, variable junction leakage (VJL), is induced by applying hole-accumulation bias to the gate of the MOSFET. This result indicates that a hole captured in the gate oxide near the silicon surface influences the channel surface potential and causes fluctuation in generation-recombination (g-r) current generated at interface states. The fluctuation in g-r current is observed as VJL. It was also found that occurrence rate of VJL increases under hot-carrier stress. On the basis of these results, a model for VJL that can more concretely explain the mechanism of VJL quantitatively was developed.

Comprehensive study on vth variability in silicon on Thin BOX (SOTB) CMOS with small random-dopant fluctuation: Finding a way to further reduce variation

Thin drift layers were used to realize n-channel 4H-SiC IGBTs with an extremely low switching loss. The thickness of a drift layer was 60 μm, which was designed for a blocking voltage of 6.5 kV. An on-voltage of 5.4 V was obtained at a collector current of 100 A/cm2 and the specific differential on-resistance at 100 A/cm2 was 20 mΩcm2 at room temperature, indicating proper bipolar operation. A switching evaluation of the SiC IGBTs was performed with a bus voltage of 3.6 kV and a load current of 10 A, and a turn-off loss of 1.2 mJ was obtained. This turn-off loss is very small compared to the values in the current literatures, and was estimated to be an over 80% reduction. The series operation of thin-drift-layer 6.5 kV SiC IGBTs can ensure a lower switching loss than the single operation of higher blocking voltage devices in power conversion systems.

Mechanism of random telegraph noise in junction leakage current of metal-oxide-semiconductor field-effect transistor

Threshold-voltage (Vth) variation of silicon on thin buried oxide (SOTB) complementary metal–oxide–semiconductor (CMOS) transistors and the impact of reducing the variation on leakage current were studied. Both reduction of impurity concentration in the silicon-on-insulator (SOI) layer and suppression of short-channel effect without the halo implantation were essential for reducing the Vth variation. Using a metal-gate was also effective. The standard deviation of Vth (σVth) for SOTB with fully silicided (FUSI) metal gate was half that for the bulk with the same gate size. This improvement can reduce the off-state leakage current summed over a large number of transistors by half in the 65-nm technology. With further scaling of the gate length, this effect can be enhanced. The SOTB of small σVth has a strong impact on reducing leakage current in highly scaled LSI.

6.5 kV n-Channel 4H-SiC IGBT with Low Switching Loss Achieved by Extremely Thin Drift Layer

Based on the experience with silicon (Si) devices, some characteristics of silicon carbide (SiC) devices are likely to be misunderstood. In this paper, studies on channel mobility, time dependent dielectric breakdown (TDDB), and negative bias temperature instability (NBTI) in 4H-SiC MOSFETs are reviewed. Through the discussions, it is indicated that SiC-based models, such as local band gap modulation, and models for the relationship between defect energy state and SiC band gap are effective to understand the above characteristics.

Evaluation of Threshold-Voltage Variation in Silicon on Thin Buried Oxide Complementary Metal–Oxide–Semiconductor and Its Impact on Decreasing Standby Leakage Current

We propose a modified model for interface-state charges to comprehend the device characteristics of 4H-SiC MOSFETs. Device characteristics, such as channel current and channel capacitance, and their dependence on temperature were intuitionally expected by regarding interface-state charges at the conduction band edge as stagnation. We also found that the observed mobility was underestimated through conventional experimental methods compared with actual channel mobility due to stagnant carriers.

Effects of interface properties in SiC MOSFETs on reliability

A novel complex MOSFET that enabled a steeper subthreshold swing than the theoretical diffusion-based limit was developed. By forming a tunnel junction in a drain diffusion layer of the MOSFET, multiple devices, i.e., a tunnel-injection bipolar transistor, a resistor, and a MOSFET, were able to be successfully integrated in a single scaled MOSFET. Applying an enhanced input signal, Vg, to the tunnel junction, stimulated tunneling carrier injection, which resulted in a steep subthreshold swing even if the supply voltage was small (∼0.2 V).

Modified Interface State Charge Model for 4H-SiC Power MOSFETs

The Random Telegraph Noise (RTN) in an advanced Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is considered to be triggered by just one electron or one hole, and its importance is recognised upon the aggressive scaling. However, the detailed nature of the charge trap remains to be investigated due to the difficulty to find out the exact device, which shows the RTN feature over statistical variations. Here, we show the RTN can be observed from virtually all devices at low temperatures, and provide a methodology to enable a systematic way to identify the bias conditions to observe the RTN. We found that the RTN was observed at the verge of the Coulomb blockade in the stability diagram of a parasitic Single-Hole-Transistor (SHT), and we have successfully identified the locations of the charge traps by measuring the bias dependence of the RTN.

CxFET: A novel steep subthreshold swing CMOS featuring a tunnel-injection bipolar transistor and MOSFET device complex

We designed, fabricated and evaluated 6.5 kV SiC PiN diodes. In order to suppress process-induced basal plane dislocation (BPD) in SiC PiN diodes, we improved the fabrication processes. The Ir-Vr measurements showed that the breakdown voltage was over 9 kV at room temperature (25 °C). The leakage currents (Ileak) at 6.5 kV are as low as 5.9×10-6 mA/cm2 (25 °C) and 9.7×10-5 mA/cm2 (150 °C). The maximum recovery loss among our switching test results was 6.7 mJ at 150 °C, 60 A. Moreover, the diodes fabricated on BPD-free area are very stable during applying 20 A current for 8~1000 h. Photoluminescence (PL) observation and KOH etching indicated that no BPD generated during improved fabrication processes.