Akio Shima

A model for the segregation and pileup of boron at the SiO2/Si interface during the formation of ultrashallow p+ junctions

We have quantitatively investigated how boron segregates to regions close to the surface, and what controls this phenomenon, using x-ray photoelectron spectroscopy, Fourier transform infrared spectroscopy and backside secondary ion mass spectrometry measurement techniques. We found that, contrary to the equilibrium segregation, the pileup of boron is mainly on and within 0.6 nm of the Si side of the interface, and that there is no difference between the kind of encapsulation. This also suggests that the pileup of boron is mainly on the Si side, and implies that the main factor in this segregation is the existence of the Si surface. From the viewpoint of device fabrication, this result seems to be useful in terms of the fabrication of sidewalls. The possibility of boron pileup to occurring in the interstitial state was also shown. Our results suggested a way of looking at dopant profiles by predictive computer modeling.

Ultra-Shallow Junction Formation by Non-Melt Laser Spike Annealing and its Application to Complementary Metal Oxide Semiconductor Devices in 65-nm Node

We activated source/drain junctions of complementary metal oxide semiconductor (CMOS) by simply replacing rapid thermal annealing (RTA) in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers, unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better Vth roll-offs and larger drain currents compared to those formed by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.

Scalable 3-D vertical chain-cell-type phase-change memory with 4F2 poly-Si diodes

A three-dimensional (3-D) vertical chain-cell-type phase-change memory (VCCPCM) for next-generation large-capacity storage was developed. The VCCPCM features formation of memory holes in multi-layered stacked gates by using a single mask and a memory array without a selection transistor. As a result of this configuration, the number of process steps for fabricating the VCCPCM is reduced. The excellent scalability of the VCCPCMs new phase-change material makes it possible to reduce the cell size beyond the scaling limit of flash memory. In addition, a poly-silicon selection diode makes it possible to reduce the cell factor to 4F2. Consequently, relative cost of the VCCPCM compared to 3-D flash memory is reduced to 0.2.

Dopant profile engineering of CMOS devices formed by non-melt laser spike annealing

We optimized the halo profile and deep source/drain junction profile of the devices that were fabricated by non-melt laser spike annealing (LSA). The optimized devices achieved 10%- and 20%-better performance compared to those by the conventional LSA and rapid thermal annealing (RTA), respectively. The hot carrier degradation was also reduced to an RTA-comparable level by the halo optimization. From these results we concluded that the dopant profile engineering specific to LSA is a key to obtaining good device performance and that the devices by the optimized LSA process are the most promising for hp65-node and beyond.

Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS

We activated source/drain junctions of CMOS by simply replacing RTA in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better Vth roll-offs and larger drain currents compared to those by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.

Ultrashallow junction formation by self-limiting LTP and its application to sub-65-nm node MOSFETs

We have developed a novel laser thermal process that dramatically enhances laser exposure windows by controlling the heating process in a self-limiting way. Key technology is realized by introducing a new process combination of preamorphization implantation and a heat absorber with a phase switch layer, and by optimizing them. The V/sub th/ rolloffs of MOSFETs formed by this method were remarkably improved compared to those by rapid thermal annealing when offset-spacer and halo-implantation processes were not applied. Its effectiveness was also verified in 50-nm gate complementary metal-oxide semiconductor devices for the first time by confirming that the drain current increased with laser fluence beyond the conventional exposure limit.

Self-limiting laser thermal process for ultra-shallow junction formation of 50-nm gate CMOS

We have developed a novel LTP (laser thermal process) that dramatically enhances the laser exposure window by controlling the heating process in a self-limiting way (SL-LTP). The Vth roll-offs of MOSFETs formed by this method were remarkably improved compared to those by RTA when offset-spacer and halo-implantation processes were not applied. Its effectiveness was also verified in 50-nm gate CMOS devices for the first time by confirming that the drain current increased with laser fluence beyond the conventional exposure limit.

Enhancement of Drain Current in Planar MOSFETs by Dopant Profile Engineering Using Nonmelt Laser Spike Annealing

We investigated the effect of dopant profile engineering in planar MOSFETs, in which activation annealing was done using only nonmelt laser spike annealing (LSA). Device performance was 10% and 20% better compared to that when conventional LSA and rapid thermal annealing (RTA) are used, respectively. We achieved this by reengineering the following: 1) angle implantation in the extension of an nFET; 2) germanium preamorphization implantation in the extension of a pFET; 3) halo implantation with lower energy and smaller tilt angle; 4) deep source/drain by two-step implantation, and 5) counter implantation adjusted to the halo conditions. Hot carrier degradation was also reduced to an RTA-comparable level by halo profile engineering. Thus, we show that a submillisecond LSA is a promising technique for the fabrication of ultrashallow junctions for the 45-nm technology node and beyond and that a dopant profile engineering taking into account the minimal diffusion length of LSA is required to bring out the best device performance.

6.5 kV n-Channel 4H-SiC IGBT with Low Switching Loss Achieved by Extremely Thin Drift Layer

Thin drift layers were used to realize n-channel 4H-SiC IGBTs with an extremely low switching loss. The thickness of a drift layer was 60 μm, which was designed for a blocking voltage of 6.5 kV. An on-voltage of 5.4 V was obtained at a collector current of 100 A/cm2 and the specific differential on-resistance at 100 A/cm2 was 20 mΩcm2 at room temperature, indicating proper bipolar operation. A switching evaluation of the SiC IGBTs was performed with a bus voltage of 3.6 kV and a load current of 10 A, and a turn-off loss of 1.2 mJ was obtained. This turn-off loss is very small compared to the values in the current literatures, and was estimated to be an over 80% reduction. The series operation of thin-drift-layer 6.5 kV SiC IGBTs can ensure a lower switching loss than the single operation of higher blocking voltage devices in power conversion systems.

Quantum confinement effect for efficient hole injection in MONOS-type nonvolatile memory-the role of ultrathin i-Si/P + poly-Si stacked gate structure fabricated by laser spike annealing

A novel hole injection method is proposed for fast and damage-free erasing operation in MONOS-type nonvolatile memory. Ultrathin intrinsic Si (i-Si) layer at the interface between gate dielectrics and P+ poly-Si gate produces quantum confinement level of hole. This lowers effective band offset, thus, significantly increases hole tunneling probability from the gate electrode. By applying the novel gate structure to MONOS cells, we successfully demonstrate memory operation with 100 times faster erase speed and larger memory window than conventional gate.