Hirozi Yamada

A 1-GHz-clock Josephson microcomputer system

A 1-GHz-clock Josephson microcomputer system was developed to demonstrate the possibility of a high-speed superconducting computer system. It consists of a 4-b data processor chip and a 1-kb RAM chip. For the fabrication of these Josephson integrated circuits, a cross-shaped Nb-AlO/sub x/-Nb Josephson junction process was developed in order to realize small junction size and improve critical current uniformity, and has made fabrication of LSIs with several thousand gates possible. A latchup-free DC flip-flop is an important element in the high-speed Josephson logic and memory circuits, having been applied to an all-DC-powered Josephson RAM with asynchronous access capability. A low-inductance chip-to-chip carrier is an architectural and design concept for the Josephson computers 1-GHz-clock operation, suppressing the crosstalk between the AC power and the output signals. Each chip is 7 mm square and is fabricated using a 2.5- mu m-rule Nb-AlO/sub x/-Nb junction process. The chips are connected on a superconducting carrier by solder bumps in a die size of 15 mm by 25 mm. The system is constructed from 8123 Josephson interferometer devices and is operable in a 1-ns cycle with 50-mW power dissipation.

A 4-bit Josephson data processor chip

The authors describe a 4-bit Josephson data processor chip featuring on-chip control and data paths and near-GHz capability. It is a closed, stand-alone chip comprising a 4-bit data path and a control path and is aimed at high-speed digital signal processing. The die is 0.5 mm square, including pads, is fabricated using 2.5- mu m-rule Nb/AlO/sub x//Nb technology, and consists of 8454 Josephson junctions and 9027 resistors. The cross-shaped junction structure realizes critical current scattering of +or-6%, and a junction characteristic voltage V/sub m/ of 50 mV. A block diagram of the Josephson data processor is shown.<<ETX>>

Fabrication and characteristics of NbN-based Josephson junctions for logic LSI circuits

The characteristics of a 1.5 μm square NbN-based Josephson junction were investigated and improved to make large scale application of these junctions to logic LSI circuits possible. An amorphous-like Si thin film was newly examined in order to define a junction area consistent with the pattern size of the resist mask. A Nb-oxide barrier was formed on a NbN base electrode by rf plasma cleaning and oxidation. The low leakage current (the characteristic voltage Vm, that corresponds to converting the leak into the maximum junction currents, being larger than 40 mV) and the small critical current variation were achieved by low rf-voltage plasma cleaning. By using Si-insulating layers and optimizing surface-cleaning conditions, the maximum critical current variation was reduced within ±12% for 850 junctions. The change in the normal tunneling resistance R nn due to heat-treating below 200 °C was kept within ±5%. To confirm the feasibility of applying the junctions to logic LSIs, a 3K-logic-gate array was fabricated using about 23,000 junctions and its operation was successfully demonstrated.

Optical input/output interface system for Josephson junction integrated circuits

An optical input/output interface system for a Josephson junction integrated circuit is fabricated and tested. The system consists of a superconducting optical detector, a dc powered Josephson circuit, a dc powered Josephson high voltage circuit, a liquid-He-cooled semiconductor amplifier, and a liquid-He-cooled semiconductor laser. Features of the system are use of an ultrathin NbN film for the optical detector and adoption of the dc powered Josephson circuits for logic operation circuits. Correct optical output signal is detected by a liquid-He-cooled semiconductor photodiode. The optical input/output interface has the advantage of low heat penetration and low crosstalk compared to the interface using conventional coaxial lines. Moreover, dc powered Josephson circuits have an advantage of low crosstalk from power supply lines compared to conventional Josephson circuits, which are driven by ac supply current.<<ETX>>

Design and operation of a Quantum Flux Parametron bit-slice ALU

The design of Quantum Flux Parametron (QFP) majority logic circuits presents a number of unique constraints. For example, interconnects must be kept short and have a common small inductance. The former suggests that the bit-slice architecture is well suited to QFP circuits. In order to test this conjecture, a suitably complex logic circuit was designed and a small part of it was fabricated. A design for a 16-function bit-slice arithmetic-logic unit (ALU) was found that satisfied the constraints. It can compute on n-bit operands in 2n+4 QFP stages. A reduced version of the bit-slice ALU cell, containing 30 QFPs, was fabricated and successfully tested at low speed. The design experience showed that complex combinatorial QFP logic circuits are possible. Larger circuits will be feasible with computer-aided tools.<<ETX>>

An all DC-powered Josephson logic circuit

A novel DC-powered Josephson circuit is reported. An improved HUFFLE-type DC flip-flop with a parallel resistor, to prevent hang-up, is constructed by combinational circuits as well as sequential circuits. The basic device is a vertical type two-junction interferometer with only three-metal layers. The design rule is 2.5 mu m. High junction-current density allows for a wide operating margin even with a low inductance load. Basic circuit function test elements have been completed. The DC flip-flop with excess gate current works as a GHz range VCO (voltage controlled oscillator) for internal clock generation. The speedup junction successfully accelerated the switching speed. The ring-oscillator showed a minimum gate delay of 11.3 ps. >

A 1-GIPS Josephson data processor

A 4-b data processor with 16-instruction set and 1-kb external-RAM access capability has been designed, fabricated, and tested. Each instruction is treated by a three-stage pipeline of instruction fetch, data fetch, and decode/execute. The chip is operable under a 1-GHz clock, and it has a peak performance of 1 GIPS. The fabrication process is 2.5- mu m-rule Nb/AlO/sub x//Nb. An interface circuit to access the all DC-powered 1-kb external-RAM chip is installed. The AC power is utilized with both polarities in each of the four blocks, thus realizing an eightfold serial power supply. Power consumption is 40 mW. Half of the function tests have been completed at low frequency (10 kHz). Part of the processor operated at 1 GHz. >