Hisashi Saito

Submicron InP/InGaAs Composite-Channel Metal?Oxide?Semiconductor Field-Effect Transistor with Selectively Regrown n+-Source

We have demonstrated an InP/InGaAs composite-channel metal–oxide–semiconductor field-effect transistor with a selectively regrown n+-InGaAs source/drain formed by metal organic vapor-phase epitaxy. A 150-nm-long channel was fabricated using a dummy gate and by laterally buried regrowth in the channel undercut. The gate stack was formed after regrowth by replacing the dummy gate. The carrier density of the regrown layer was 4.9×1019 cm-3. The maximum drain current at a drain voltage Vd = 1 V and a gate voltage Vg = 3 V was 0.93 mA/µm and the maximum transconductance was 0.53 mS/µm at Vd = 0.65 V.

Fabrication of Vertical InGaAs Channel Metal–Insulator–Semiconductor Field Effect Transistor with a 15-nm-Wide Mesa Structure and a Drain Current Density of 7 MA/cm2

We proposed a vertical InGaAs channel metal–insulator–semiconductor field effect transistor (MISFET) with an ultranarrow mesa structure, an undoped channel, and a heterostructure launcher. With the aim of obtaining a narrow mesa structure, we proposed the concept of performing selective undercut etching after dry etching. We fabricated the proposed device with a 60-nm-long and 15-nm-wide channel mesa structure. In the fabricated device, the observed drain current density was 1.1 A/mm. Because the channel mesa width was 15 nm, the drain current density per unit area was 7 MA/cm2. Thus, a high current density was achieved for an ultranarrow mesa structure.

71 mV/dec of sub-threshold slope in vertical tunnel field-effect transistors with GaAsSb/InGaAs heterostructure

We fabricated a vertical tunnel field-effect transistor (TFET) with a GaAsSb/InGaAs heterojunction using a 5-nm-thick Al2O3 dielectric. The 26-nm width of the narrow channel mesa structure was confirmed using citric acid solution. The minimum sub-threshold slope (SS) was 71 mV/dec. On the basis of our simulated and experimental results, the SS was estimated to be 54 mV/dec for an effective oxide thickness (EOT) of 1 nm.

Improvement in Gate Insulation in InP Hot Electron Transistors for High Transconductance and High Voltage Gain

In this paper, the device characteristics of an InP hot electron transistor with improved gate insulation are reported. The breakdown voltage of the gate was increased from 0.5 to 2.5 V by increasing the distance between the gate and the electron transport region. Consequently, the appropriate gate bias at which a clear transconductance peak could be observed was applied. The transconductance was increased from 55 to 130 mS/mm. When the output conductance was reduced, the open circuit voltage gain was about 10.

Vertical InGaAs Channel Metal–Insulator–Semiconductor Field Effect Transistor with High Current Density

A high-speed transistor operation is expected from using an undoped channel region. We propose a vertical InGaAs-channel metal–insulator– semiconductor field effect transistor (MISFET) with an ultra-narrow mesa structure, an undoped channel, and a heterostructure launcher. According to a Monte Carlo simulation, a cutoff frequency of 1.5THz is expected when a 20-nm-wide mesa structure, a 60-nm-long channel, and a 5MA/cm 2 drain current density are achieved. We fabricated an ultra-narrow mesa structure by using selective undercut etching. In the fabricated device, the channel mesa was 15nm wide, and the observed drain current density was 0.95A/mm. Because the channel mesa width was 15nm, the drain current density per unit area was 6.3MA/cm 2 . A high current density was achieved for a short charging time. By comparing the drain current density of the 60-nm-long channel device with that of a 100-nm-long channel device, we inferred that quasi-ballistic transportation can be achieved in our devices. # 2011 The Japan Society of Applied Physics

InP/InGaAs hot electron transistors with insulated gate

Elimination of the base layer in conventional hot electron transistor has possibility to minimize the scattering in the propagation. In previous study, we fabricated InP/InGaAs hot electron transistors without a doped layer in the propagation region by fabricating a 25-nm-wide emitter and Schottky gate electrodes located at both sides of an emitter mesa. However, there were some problems in fabricated device. To solve these observed problems, we proposed and fabricated a new structure with hot electrons propagating only in the intrinsic semiconductor. An insulated gate was introduced in hot electron transistors, in which hot electrons are propagated only in the intrinsic region after extraction from a heterostructure launcher. Clear collector current modulation by the insulated gate and a current density of 160 kA/cm2 were confirmed.

Reduction of Output Conductance in Vertical InGaAs Channel Metal–Insulator–Semiconductor Field-Effect Transistor Using Heavily Doped Drain Region

In this paper, the reduction in the output conductance (go) of a vertical InGaAs channel metal–insulator–semiconductor field-effect transistor (MISFET) is reported. While vertical InGaAs channel MISFETs exhibit a high drain current density, their large go is a disadvantage. Monte Carlo simulation suggests that the large go might be caused by conduction band bending due to many space charges between the gate and drain. To prevent conduction band bending, a device in which the gate electrode overlaps with the drain region was proposed and fabricated. Consequently, go was decreased from 3.2 to 1 S/mm.

Vertical InGaAs-MOSFET with hetero-launcher and undoped channel

We propose a vertical InGaAs MOSFET with hetero-launcher and undoped channel. In a previous trial of this particular MISFET innovation, the number of devices that achieved current modulation by gate bias was only 10% of the total number of the fabricated devices. This poor result was caused by loss of thickness of the gate dielectric. In the new version of this device, the gate stuck was fabricated by successive depositions of SiO2 and gate metal. The number of devices achieving current modulation by gate bias now increased to 50% of the total number of the fabricated devices. Moreover, the drain current density was observed to increase from 100 mA/mm to 270 mA/mm.

Submicron InP/InGaAs composite channel MOSFETs with selectively regrown N + -source/drain buried in channel undercut

We demonstrated a high-mobility InP 5 nm/InGaAs 12 nm composite channel MOSFET with MOVPE regrown n⁺-source/drain region for low series resistance and high source injection current. A gate dielectric was SiO<inf>2</inf> and thickness was 20 nm. A carrier density of regrown InGaAs source/drain layer was over 4 × 10¹⁹ cm⁻³. In the measurement of submicron (= 150 nm) device, the drain current was 0.93 mA/µm at V<inf>g</inf> = 3 V, V<inf>d</inf> = 1 V and the peak transconductance was 0.53 mS/µm at V<inf>d</inf> = 0.65 V, respectively. The channel length dependence of transconductance indicated the good relativity.

Selective undercut etching for ultra narrow mesa structure in vertical InGaAs channel MISFET

It is important for shrinking the mesa width of a channel region in a vertical InGaAs channel MISFET for carrying out high-speed operation and for obtaining a steep sub-threshold slope. Therefore, we introduced selective undercut etching after the dry etching of the mesa structure. In the fabricated device with 60-nm-long channel, the channel mesa width became 15 nm. The maximum drain current density at V<inf>ds</inf> = 0.75 V and V<inf>g</inf> = 1.5 V was 1.1 A/mm and the maximum transconductance at V<inf>ds</inf> = 0.75 V and V<inf>g</inf> = 0 V was 530 mS/mm.