Kazuhito Furuya

Lateral confinement in a resonant tunneling transistor with a buried metallic gate

We have fabricated a resonant tunneling transistor by epitaxial overgrowth over a tungsten grating placed 30 nm above a GaAs/GaInP semiconductor, double barrier, resonant tunneling heterostructure. The Schottky depletion around the buried metal contacts controls the current to a vertical transistor channel. The lateral extension of this channel is defined by a square opening in the grating with a side length of 1.4 μm, which corresponds to a sub-μm electrical width. The transport properties at 20 K show a fine structure in the resonant tunneling characteristics, and it is affected by the gate bias. These effects are discussed in terms of lateral quantum confinement in the transistor channel defined.

Proposal of buried metal heterojunction bipolar transistor and fabrication of HBT with buried tungsten

We propose a buried metal heterojunction bipolar transistor (BM-HBT), in which buried metal in the collector layer could reduce the total base-collector capacitance. To show the possibility of making a BM-HBT, we fabricated an InP-based HBT with buried tungsten mesh replacing the subcollector layer, where tungsten mesh works as a Schottky collector electrode. A flat heterostructure on the InP collector layer of the buried tungsten mesh was confirmed by a cross-sectional SEM view. A DC current gain of 12 was measured from the common-emitter collector I-V characteristics.

Fabrication and transport properties of 50-nm-wide Au/Cr/GaInAs electrode for electron wave interference device

Abstract To conduct Youngs double slit experiment using a semiconductor, fabrication techniques for 80 to 100-nm-period fine electrodes with 30 to 40-nm thickness are reported. To obtain a resist pattern suitable for the lift-process, we used a double-layer resist with ZEP-520 and PMMA. The mixing of C60 into both layers and rinsing by perfluorohexane (PFH) prevented pattern collapse. As a result, a Au/Cr pattern with a 80-nm period over 30-nm steps was obtained. Using the developed process, we fabricated a device for observing the interference pattern. Unfortunately, the collector current from each electrode was not uniform. Moreover, the current showed anomalous behavior. The current occasionally converged in two different points and sudden jumps from the lower converged point to the upper converged point were also observed in time-dependent measurements. Such anomalous behavior might be explained in terms of a change in the ionization of an impurity near the metal–semiconductor interface.

Design and Experimental Characteristics of n-Si/CaF2/Au Hot Electron Emitter for Use in Scanning Hot Electron Microscopy

For scanning hot electron microscopy experiments, n-Si/CaF2/Au hot electron emitters were designed and fabricated to characterize the emission properties. A self-consistent method was used in analyzing the hot electron energy and the tunneling current density while considering the quantum mechanical effects in the space-charge region. By comparison of the theoretical calculations with the experimental results for current density, the tunneling electron effective mass of CaF2 is estimated to be about 0.3m0. This material structure can provide an electron current density of more than 10 A/cm2 at the hot electron energies of 2.9 eV or 3.7 eV by selecting the thickness of CaF2 to be 3 nm or 4 nm, respectively, for the electron density of 8×1019 cm-3, or at 3.2 eV or 3.4 eV by selecting the electron density of 1019 cm-3 or 2×1018 cm-3, respectively, for the insulator thickness of 3 nm.

Shortening of Detection Time for Observation of Hot Electron Spatial Distribution by Scanning Hot Electron Microscopy

The scanning hot electron microscope (SHEM) is a tool to observe non-thermal- equilibrium electrons under the surface of a solid, and it enables us to study the hot electron diffraction pattern caused by a small structure in the propagation layer. To observe the hot electron spatial distribution by SHEM, the detection time must be shortened. The reduction of the noise current including vibrational noise is investigated comprehensively. By the reduction of noise, in particular, that of nonstationary noise with digital measurements, the hot electron current was detected in 30 s, 1/20 of the measurement time reported previously.

Lateral current confinement in selectively grown resonant tunneling transistor with an embedded gate

We report on fabrication and measurements of a selectively grown vertical resonant tunneling transistor with lateral current constriction. A GaInP/GaAs/GaInP, 3/9/3 nm, double barrier structure is epitaxially grown over a grating of tungsten (W) wires, where the Schottky depletion around the embedded wires creates a semi-insulating layer. The vertical current in the device passes the semi-insulating region through a designed opening (1×1μm2) in the grating, which, taking the depletion region into account, gives a transistor with an electrical area of well below 1μm2. Current–voltage (I–V) measurements at 4 K show a multitude of current peaks that respond strongly to the gate voltage applied to the metal grating. From the gate response and the small lateral area, we believe that these peaks arise from lateral confinement effects.

Peak Width Analysis of Current–Voltage Characteristics of Triple-Barrier Resonant Tunneling Diodes

We studied the peak width of current vs voltage (I–V) characteristics of triple-barrier resonant tunneling diodes (TBRTDs) experimentally and theoretically. A GaInAs/InP TBRTD was fabricated by organo metallic vapor phase epitaxy (OMVPE). A theory of I–V characteristics of TBRTDs was developed by taking the structural inhomogeneity into account to explain the experimental peak width. The fluctuation of the well width in a TBRTD grown by OMVPE was estimated as two atomic layers.

Toward nano-metal buried structure in InP – 20 nm wire and InP buried growth of tungsten

Abstract Toward nano-metal buried structure in InP, we studied the fabrication process of nano-tungsten wire and the InP buried growth of tungsten stripes. A tungsten wire with a 20 nm width was fabricated by the proposed metal-stencil liftoff, in which gold/chromium and SiO 2 replace resist to prevent thermal deformation in a conventional liftoff process. The buried growth of tungsten stripes with 1 μ m widths and 2 μ m pitch by organometallic vapor phase epitaxy (OMVPE) was studied. Tungsten stripes were buried under the flat InP layer of 1.1 μ m thickness, and the ratio of grown InP thickness to buried tungsten width was about 1.

Gated Tunneling Structures with Buried Tungsten Grating Adjacent to Semiconductor Heterostructures

A tungsten (W) grating was fabricated and embedded in GaAs by MOVPE (metal organic vapor phase epitaxy) with the aim of realizing novel applications of ultrafine metal electrodes within semiconductor nanodevices. A combination of W grating and a semiconductor single heterobarrier was used to control the vertical current through the structure based on an effective barrier height modulation controlled by the Schottky depletion around the metal. Transistor operation was observed at room temperature and the mode of operation discussed. Moreover, a gated resonant tunneling transistor was demonstrated at 20 K by integrating GaInP/GaAs double barriers and W grating, including a 1.4 ×1.4 µm2 opening window, to form a vertical channel. The peak-to-valley current ratios were modulated by the gate bias, and fine features due to the lateral potential constriction were observed directly in the current-voltage characteristics.

Reduction of Base-Collector Capacitance in Submicron InP/GaInAs Heterojunction Bipolar Transistors with Buried Tungsten Wires

A buried metal heterojunction bipolar transistor with a 0.5-µm-wide emitter was fabricated by electron-beam lithography, in which three tungsten wires of 100 nm width, 100 nm height and 200 nm period were buried in the InP collector layer. For the device with an emitter area of 0.5×2.5 µm2, total base-collector capacitance was reduced to about 30% of that calculated from the physical dimensions of a conventional heterojunction bipolar transistor, and a current gain cutoff frequency of 86 GHz and a maximum oscillation frequency higher than 135 GHz were obtained.