Hisatada Miyatake

A design for high-speed low-power CMOS fully parallel content-addressable memory macros

Described is a design for high-speed low-power-consumption fully parallel content-addressable memory (CAM) macros for CMOS ASIC applications. The design supports configurations ranging from 64 words by 8 bits to 2048 words by 64 bits and achieves around 7.5-ns search access times in CAM macros on a 0.35-/spl mu/m 3.3-V standard CMOS ASIC technology. A new CAM cell with a pMOS match-line driver reduces search rush current and power consumption, allowing a NOR-type match-line structure suitable for high-speed search operations. It is also shown that the CAM cell has other advantages that lead to a simple high-speed current-saving architecture. A small signal on the match line is detected by a single-ended sense amplifier which has both high-speed and low-power characteristics and a latch function. The same type of sense amplifier is used for a fast read operation, realizing 5-ns access time under typical conditions. For further current savings in search operations, the precharging of the match line is controlled based on the valid bit status. Also, a dual bit switch with optimized size and control reduces the current. CAM macros of 256/spl times/54 configuration on test chips showed 7.3-ns search access time with a power-performance metric of 131 fJ/bit/search under typical conditions.

DRAM macros for ASIC chips

DRAM macros in 4-Mb (0.8-/spl mu/m) and 16-Mb (0.5-/spl mu/m) DRAM process technology generations have been developed for CMOS ASIC applications. The macros use the same area efficient one transistor trench cells as 4-Mb (SPT cell) and 16-R Mb (MINT cell) DRAM products. It is shown that the trench cells with capacitor plates by the grounded substrate are ideal structures as embedded DRAMs. The trench cells built entirely under the silicon surface allow cost effective DRAM and CMOS logic merged process technologies. In the 0.8-/spl mu/m rule, the DRAM macro has a 32-K/spl times/9-b configuration in a silicon area of 1.7/spl times/5.0 mm/sup 2/. It achieves a 27-ns access and a 50-ns cycle times. The other DRAM macro in the 0.5-/spl mu/m technology is organized in 64 K/spl times/18 b. It has a macro area of 2.1/spl times/4.9 mm and demonstrated a 23-ns access and a 40-ns cycle times. Small densities and multiple bit data configurations provide a flexibility to ASIC designs and a wide variety of application capabilities. Multiple uses of the DRAM macros bring significant performance leverages to ASIC chips because of the wide data bus and the fast access and cycle times. A data rate more than 1.3 Gb/s is possible by a single chip. Some examples of actual DRAM macro embedded ASIC chips are shown. >

A parallel processing chip with embedded DRAM macros

A combined DRAM and logic chip has been developed for massively parallel processing (MPP) applications. A trench cell 4-Mb CMOS DRAM technology is used to fabricate the chip with an additional third-level metal layer. The 5-V 0.8-/spl mu/m technology merges 100-K gate custom logic circuits and 4.5-Mb DRAM onto a 14.7/spl times/14.7 mm/sup 2/ die. The DRAM design is based on a 32-K/spl times/9-b (288-Kb) self-consistent macro form. It has independent address inputs, data I/O ports, access control circuits, and redundancy fuses and elements. The logic part of the chip consists of eight 16-b CPUs and some broadcast logic circuits. Each CPU and two DRAM macros (64-KB) comprise a processing element (PE), and hypercube connections among eight PEs are made for the scalable MPP capability. Each chip delivers 50-MIPS of performance at 2.7 W.

Optimizing write current and power dissipation in MRAMs by using an astroid curve

Analytical expressions of minimum electric current and power dissipation, and bit line and word line currents that produce them, for writing data into magnetic tunnel junction (MTJ) magnetoresistive random access memory (MRAM) cells are derived with the assumption that an asteroid curve can be applied to all MTJs in a memory cell array. The expressions contain word length, that is, the number of bits per word, and parasitic resistances of the write word line and bit line (which are important design parameters of memory cell arrays) and distances between the write currents and the free magnetic layer for data storage (which are important structural parameters of MTJ cells). They provide quantitative MRAM design guidelines and help to understand current and power behavior. For example: 1) the current along the bit lines should be decreased and the current along the write word line should be increased as the word length increases; 2) the word line currents for the minimum total current and power dissipation have maximum values at certain word line distances from the free layer; and 3) the minimum current and power have tendencies to saturate as the word length increases. Plots of the expressions exemplify the current and power dissipation behavior and dependence on the parameters related to the design of MRAM and MTJ cells.