Toshio Sunaga

DRAM macros for ASIC chips

DRAM macros in 4-Mb (0.8-/spl mu/m) and 16-Mb (0.5-/spl mu/m) DRAM process technology generations have been developed for CMOS ASIC applications. The macros use the same area efficient one transistor trench cells as 4-Mb (SPT cell) and 16-R Mb (MINT cell) DRAM products. It is shown that the trench cells with capacitor plates by the grounded substrate are ideal structures as embedded DRAMs. The trench cells built entirely under the silicon surface allow cost effective DRAM and CMOS logic merged process technologies. In the 0.8-/spl mu/m rule, the DRAM macro has a 32-K/spl times/9-b configuration in a silicon area of 1.7/spl times/5.0 mm/sup 2/. It achieves a 27-ns access and a 50-ns cycle times. The other DRAM macro in the 0.5-/spl mu/m technology is organized in 64 K/spl times/18 b. It has a macro area of 2.1/spl times/4.9 mm and demonstrated a 23-ns access and a 40-ns cycle times. Small densities and multiple bit data configurations provide a flexibility to ASIC designs and a wide variety of application capabilities. Multiple uses of the DRAM macros bring significant performance leverages to ASIC chips because of the wide data bus and the fast access and cycle times. A data rate more than 1.3 Gb/s is possible by a single chip. Some examples of actual DRAM macro embedded ASIC chips are shown. >

A parallel processing chip with embedded DRAM macros

A combined DRAM and logic chip has been developed for massively parallel processing (MPP) applications. A trench cell 4-Mb CMOS DRAM technology is used to fabricate the chip with an additional third-level metal layer. The 5-V 0.8-/spl mu/m technology merges 100-K gate custom logic circuits and 4.5-Mb DRAM onto a 14.7/spl times/14.7 mm/sup 2/ die. The DRAM design is based on a 32-K/spl times/9-b (288-Kb) self-consistent macro form. It has independent address inputs, data I/O ports, access control circuits, and redundancy fuses and elements. The logic part of the chip consists of eight 16-b CPUs and some broadcast logic circuits. Each CPU and two DRAM macros (64-KB) comprise a processing element (PE), and hypercube connections among eight PEs are made for the scalable MPP capability. Each chip delivers 50-MIPS of performance at 2.7 W.

A full bit prefetch architecture for synchronous DRAM's

A high performance data path circuit design for Synchronous DRAMs (SDRAMs) is described. Data lines by second-level of metal above memory cells achieve a low power and area efficient full bit prefetch capability. An experimental 3.3-V 16-Mb SDRAM is developed based on this architecture. Since the full burst read data are latched in I/O sense amplifiers by a single CAS access, a precharge operation can start as early as two clocks before the data burst cycles begin. The early precharge function allows next RAS and CAS accesses during burst reads of the previous data. With a burst length of eight, a seamless read operation is possible for any row addresses even within the same bank. The full bit prefetch architecture enables low active power data burst operations because high frequency clock driven circuits are limited to the data path only. The SDRAM with a 1M/spl times/16-b configuration dissipates a 65-mA active current at a 100-MHz full page mode operation. >

An eight-bit prefetch circuit for high-bandwidth DRAM's

A low-power and area-efficient data path circuit for high-bandwidth DRAMs is described. For fast burst read operations, eight data per data I/O are stored in local latches placed close to sense amplifiers. As implemented in a 16-Mb synchronous DRAM (SDRAM), this 8-b prefetch circuit allows an early precharge command and a fast access time because it provides low-capacitance data lines for segmented bit-line pairs. At a column address strobe (CAS) latency of two and a burst length of four, the SDRAM demonstrates 100-MHz seamless read operations from different row addresses, because the row precharge and read access latencies are hidden during the burst cycles. The layout of the prefetch circuit is not limited by the bit-line pitch, and data path circuits are connected by a second-metal layer over the memory cells. As a result, a small chip size of 99.98 mm/sup 2/ is attained. Low-capacitance data lines and small local latches result in low active power. In a 100-MHz full-page burst mode, the SDRAM with a 1 M/spl times/16-b configuration dissipates 60 mA at 3.6 V.

A full bit prefetch DRAM sensing circuit

A DRAM sensing circuit that achieves both a fast RAS access time and a high-bandwidth burst operation is proposed. For the data burst capability of synchronous DRAMs, 256-bit-long data I/O lines are divided into eight segments. A small local latch is provided for each segment of 32 bit-line pairs to prefetch eight data out of the 256 sense amplifiers. A local buffer is connected to eight local latches through selection switches. Burst read operations, up to eight bits, are done by activating selection switches and the local buffer serially. Besides this prefetch capability, the segmented data I/O line results in very small capacitance, only 0.09 pF. The sensing scheme uses nMOS bit switches and a full Vdd precharge voltage for bit and segmented data I/O lines. Then, after sense amplifiers are turned on, only low-going bit lines are connected to the segmented data I/O lines without any voltage disturbance because of the small capacitance. The proposed circuit, therefore, realizes a high-speed RAS access, which is 16 ns faster than a conventional DRAM. A circuit layout design based on a 0.5-/spl mu/m design rule shows no area impact.

A 30-ns cycle time 4-Mb mask ROM

A 4-Mb mask ROM in a 256-Kb/spl times/16 organization is described. It is fabricated with a 1.0-/spl mu/m CMOS process, using single polysilicon, two levels of metal, and 3.0/spl times/4.4 /spl mu/m/sup 2/ X-cells. Unlike conventional ROMs, it implements a DRAM type RAS/CAS control scheme. A RAS access time of 60 ns is measured. For a fast data access, the chip has a consecutive address read mode in which the system needs to supply only a first address and subsequent addresses are generated in the ROM chip at every CAS clock. A 30-ns cycle time is demonstrated in this mode. 16-b data pins are also used for RAS/CAS multiplexed address inputs. Because of this three way pin multiplexing, the 7.5/spl times/10.5 mm/sup 2/ chip needs only 28 pins for its 400-mil SOJ package. >

Optimizing write current and power dissipation in MRAMs by using an astroid curve

Analytical expressions of minimum electric current and power dissipation, and bit line and word line currents that produce them, for writing data into magnetic tunnel junction (MTJ) magnetoresistive random access memory (MRAM) cells are derived with the assumption that an asteroid curve can be applied to all MTJs in a memory cell array. The expressions contain word length, that is, the number of bits per word, and parasitic resistances of the write word line and bit line (which are important design parameters of memory cell arrays) and distances between the write currents and the free magnetic layer for data storage (which are important structural parameters of MTJ cells). They provide quantitative MRAM design guidelines and help to understand current and power behavior. For example: 1) the current along the bit lines should be decreased and the current along the write word line should be increased as the word length increases; 2) the word line currents for the minimum total current and power dissipation have maximum values at certain word line distances from the free layer; and 3) the minimum current and power have tendencies to saturate as the word length increases. Plots of the expressions exemplify the current and power dissipation behavior and dependence on the parameters related to the design of MRAM and MTJ cells.

A variable precharge voltage sensing

A new DRAM sensing approach that uses variable precharge voltage has been developed and analyzed in simulations. It uses a voltage swing only on the bit-line connected to the accessed cell. The bit-line precharge voltage varies from one RAS cycle to the next, depending on the level of the data in the accessed cell. The reference voltage for bit-line sensing is given by a new reference-cell control circuit without using a reference-voltage generator. The current required for sensing decreases as the precharge voltage increases, resulting in reduced power without any reduction of the sensing signal. Detailed analysis shows that the sensing current is only 2/3 of that in 1/2 T/sub DD/ sensing, even in the worst case. >