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Featured researches published by Hisataka Meguro.


IEEE Transactions on Electron Devices | 1996

Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices

Seiichi Mori; Yoshiko Araki; Muneharu Sato; Hisataka Meguro; Hiroaki Tsunoda; Eiji Kamiya; Kuniyoshi Yoshikawa; Norihisa Arai; Eiji Sakagami

This paper describes the scaling limitation factors of ONO interpoly dielectric thickness, mainly considering the charge retention capability and threshold voltage stability for nonvolatile memory cell transistors with a stacked-gate structure, based on experimental results. For good intrinsic charge retention capability, either the top- or bottom-oxide thickness should be greater than around 6 nm. On the other hand, a thicker top oxide structure is preferable to minimize degradation due to defects. It has been confirmed that a 3.2 nm bottom-oxide shows detectable threshold voltage instability, but 4 nm does not. Effective oxide thickness scaling down to around 13 nm should be possible for flash memory devices with a quarter-micron design rule.


Archive | 2010

Semiconductor storage device and method for manufacturing the same

Kenji Aoyama; Hisataka Meguro; Satoshi Nagashima


Archive | 2001

Method of making non-volatile memory with polysilicon spacers

Hisataka Meguro


Archive | 2006

Method of manufacturing non-volatile semiconductor memory

Ichiro Mizushima; Hajime Nagano; Yoshio Ozawa; Hisataka Meguro; Takashi Suzuki


Archive | 2003

Nonvolatile semiconductor memory device having a memory cell that includes a floating gate electrode and control gate electrode

Fumitaka Arai; Riichiro Shirota; Toshitake Yaegashi; Akira Shimizu; Yasuhiko Matsunaga; Masayuki Ichige; Hisataka Meguro


Archive | 1997

Semiconductor device having a nitrogen doped polysilicon layer

Hideyuki Kinoshita; Hiroaki Tsunoda; Hisataka Meguro


Archive | 2003

Semiconductor memory device having memory transistors with gate electrodes of a double-layer stacked structure and method of fabricating the same

Hisataka Meguro


Archive | 2008

SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF

Kenji Kawabata; Hisataka Meguro


Archive | 2012

Method of manufacturing a memory device using fine patterning techniques

Keisuke Kikutani; Satoshi Nagashima; Hidefumi Mukai; Takehiro Kondoh; Hisataka Meguro


Archive | 2014

SEMICONDUCTOR STORAGE DEVICE AND FABRICATION METHOD THEREOF

Hiroyuki Yamasaki; Hisataka Meguro

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