Hisataka Meguro
Toshiba
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Publication
Featured researches published by Hisataka Meguro.
IEEE Transactions on Electron Devices | 1996
Seiichi Mori; Yoshiko Araki; Muneharu Sato; Hisataka Meguro; Hiroaki Tsunoda; Eiji Kamiya; Kuniyoshi Yoshikawa; Norihisa Arai; Eiji Sakagami
This paper describes the scaling limitation factors of ONO interpoly dielectric thickness, mainly considering the charge retention capability and threshold voltage stability for nonvolatile memory cell transistors with a stacked-gate structure, based on experimental results. For good intrinsic charge retention capability, either the top- or bottom-oxide thickness should be greater than around 6 nm. On the other hand, a thicker top oxide structure is preferable to minimize degradation due to defects. It has been confirmed that a 3.2 nm bottom-oxide shows detectable threshold voltage instability, but 4 nm does not. Effective oxide thickness scaling down to around 13 nm should be possible for flash memory devices with a quarter-micron design rule.
Archive | 2010
Kenji Aoyama; Hisataka Meguro; Satoshi Nagashima
Archive | 2001
Hisataka Meguro
Archive | 2006
Ichiro Mizushima; Hajime Nagano; Yoshio Ozawa; Hisataka Meguro; Takashi Suzuki
Archive | 2003
Fumitaka Arai; Riichiro Shirota; Toshitake Yaegashi; Akira Shimizu; Yasuhiko Matsunaga; Masayuki Ichige; Hisataka Meguro
Archive | 1997
Hideyuki Kinoshita; Hiroaki Tsunoda; Hisataka Meguro
Archive | 2003
Hisataka Meguro
Archive | 2008
Kenji Kawabata; Hisataka Meguro
Archive | 2012
Keisuke Kikutani; Satoshi Nagashima; Hidefumi Mukai; Takehiro Kondoh; Hisataka Meguro
Archive | 2014
Hiroyuki Yamasaki; Hisataka Meguro