Hajime Nagano

Robustness of a selective epitaxial-growth process of silicon and its application to the fabrication of a high-quality hybrid SOI wafer

Robustness of a selective epitaxial growth of silicon is demonstrated. The process window of selectivity was estimated quantitatively using the Taguchi method and signal-to-noise ratio analysis for the first time. Both the number of the silicon nuclei on the mask layer and the growth rate of silicon on a silicon substrate were investigated as the output parameters of the Taguchi method. One of the most effective process parameters for the suppression of silicon nucleation on the mask layer without retarding the growth rate of silicon is revealed to be the flow rate of SiH/sub 2/Cl/sub 2/. By calculating the number of the silicon nuclei, which could not be detected by an available measurement method, the process window of the selectivity could be determined with which a wafer with selective epitaxial silicon layer having LSI-quality could be fabricated. A high-quality silicon-on-insulator (SOI) wafer that has both an SOI region and bulk-silicon region can be obtained, and a high-quality embedded device could be realized on the SOI wafer.

SOI/Bulk Hybrid Wafer Process Using SEG (Selective Epitaxial Growth) Technique for High-End SoC Applications

1. Abstract SOI/Bulk hybrid wafer, which has both SOI regions and bulk regions, to embed both SOI device and trench capacitor memory cells in same chip was developed. Partial etching of qOI/BOX (Buried Oxide) layers and SEG (Selective Epitaxial Growth) process simply transform an SOI wafer into a high qualtty SOI/Bulk hybrid wafer. Silicon nucleation on the mask region was systematically investigated. It was proved that nucleation could be suppressed with appropriate deposition condition and mask size. The property of trench capacitor memory cells fabricated in bulk region of SOI/Bulk hybrid wafer was comparable to those for a bulk wafer.