Hitoshi Kosugi

Latest cluster performance for EUV lithography

Previously, fundamental evaluations of the Extreme Ultra Violet (EUV) lithography process have been conducted using the CLEAN TRACK ACT™ 12 coater/developer with the ASML EUV Alpha Demo Tool (ADT) at imec. In that work, we confirmed the basic process sensitivities for the critical dimension (CD) and defectivity with EUV resists. Ultimate resolution improvements were examined with TBAH and FIRM™ Extreme. Moving forward with this work, the latest inline cluster is evaluated using the ASML NXE:3100 pre-production EUV scanner and the CLEAN TRACK™ LITHIUS Pro™ -EUV coater/developer. The imec standard EUV baseline process has been evaluated for manufacturability of CD uniformity control based on half pitch (HP) 27nm and ultimate resolution studies focusing on HP 22nm. With regards to the progress of the improvement for EUV processing, we confirmed the effectiveness of several novel concepts: FIRM™ Extreme10 showed increase in ultimate resolution and improvement in line width roughness (LWR) and process window; Tokyo Electron LTD. (TEL) smoothing process for roughness reduction showed 17% improvement for line and space (L/S) patterns; and finally the new dispense method reduced patterned wafer defectivity by over 50%.

Further investigation of EUV process sensitivities for wafer track processing

As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work, processing sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and defectivity with the ADT/CLEAN TRACK ACTTM 12 lithocluster. Analysis of a five wafer batch of CDU wafers shows within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives initial insight into the process defects with the current processing conditions. From analysis of these data, its shown that while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.

CD uniformity improvement for double-patterning lithography (litho-litho-etch) using freezing process

After an analysis of the factors that causes critical dimension (CD) variation in the lithography process of the LLE (Litho-Litho-Etch) double-patterning technology that employs the freezing process, an optimum process for freezing the resist patterns to reduce the CD variation, which occurs after the 2nd litho process, was achieved. By optimizing the track parameters of freezing process, CD variation is likely to be reduced not only in the 1st resist pattern but also in the 2nd resist pattern. The optimum conditions were adopted to form patterns of 40 nm resist lines and spaces in the evaluations conducted in this paper. The formation result showed improvement of 3 sigma of the within-wafer CD uniformity of both the 1st resist pattern and the 2nd resist pattern, by about 13% and 46% respectively.

Track processing optimizations for different EUV resist platforms: preparing for a NXE:3300 baseline process

To make sure a baseline process will be ready for the evaluation of the NXE:3300, imec evaluates promising new EUV resist materials with regards to imaging, process window and line width roughness (LWR) performance. From those screening evaluations, highest performing materials meeting dose sensitivity requirements are selected to be installed on the coat/develop track. This work details the process optimization results of the different selected resist platforms with regards to full wafer processing. Evaluations are executed on the ASML NXE:3100 equipped with a laser-assisted discharge produced plasma source from XTREME technologies, and interfaced to a TEL CLEAN TRACKTM LITHIUS ProTM -EUV.

DSA hole defectivity analysis using advanced optical inspection tool

This paper discusses the defect density detection and analysis methodology using advanced optical wafer inspection capability to enable accelerated development of a DSA process/process tools and the required inspection capability to monitor such a process. The defectivity inspection methodologies are optimized for grapho epitaxy directed self-assembly (DSA) contact holes with 25 nm sizes. A defect test reticle with programmed defects on guide patterns is designed for improved optimization of defectivity monitoring. Using this reticle, resist guide holes with a variety of sizes and shapes are patterned using an ArF immersion scanner. The negative tone development (NTD) type thermally stable resist guide is used for DSA of a polystyrene-b-poly(methyl methacrylate) (PS-b-PMMA) block copolymer (BCP). Using a variety of defects intentionally made by changing guide pattern sizes, the detection rates of each specific defectivity type has been analyzed. It is found in this work that to maximize sensitivity, a two pass scan with bright field (BF) and dark field (DF) modes provides the best overall defect type coverage and sensitivity. The performance of the two pass scan with BF and DF modes is also revealed by defect analysis for baseline defectivity on a wafer processed with nominal process conditions.

Availability of underlayer application to EUV process

EUV lithography is one of the most promising technologies for the fabrication of beyond 30nm HP generation devices. However, it is well-known that EUV lithography still has significant challenges. A great concern is the change of resist material for EUV resist process. EUV resist material formulations will likely change from conventional-type materials. As a result, substrate dependency needs to be understood. TEL has reported that the simulation combined with experiments is a good way to confirm the substrate dependency. In this work the application of HMDS treatment and SiON introduction, as an underlayer, are studied to cause a footing of resist profile. Then, we applied this simulation technique to Samsung EUV process. We will report the benefit of this simulation work and effect of underlayer application. Regarding the etching process, underlayer film introduction could have significant issues because the film that should be etched off increases. For that purpose, thinner films are better for etching. In general, thinner films may have some coating defects. We will report the coating coverage performance and defectivity of ultra thin film coating.

Improvements in process performance for immersion technology high volume manufacturing

Through collaborative efforts ASML and TEL are continuously improving the process performance for the LITHIUS Pro -i/ TWINSCAN XT:1900Gi litho cluster. In previous work from this collaboration, TEL and ASML have investigated the CDU and defectivity performance for the 45nm node with high through put processing. CDU performance for both memory and logic illumination conditions were shown to be on target for ITRS roadmap specifications. Additionally, it was shown that the current defect metrology is able to measure the required defect size of 30nm with a 90% capture rate. For the target through put of 180wph, no added impact to defectivity was seen from the multi-module processing on the LITHIUS Pro -i, using a topcoat resist process. For increased productivity, a new bevel cut strategy was investigated and shown to have no adverse impact while increasing the usable wafer surface. However, with the necessity of double patterning for at least the next technology node, more stringent requirements are necessary to prevent, in the worst case, doubling of the critical dimension variation and defectivity. In this work, improvements in process performance with regards to critical dimension uniformity and defectivity are investigated to increase the customers productivity and yield for whichever double patterning scheme is utilized. Specifically, TEL has designed, evaluated and proven the capability of the latest technology hardware for post exposure bake and defect reduction. For the new post exposure bake hardware, process capability data was collected for 40nm CD targets. For defectivity reduction, a novel concept in rinse technology and processing was investigated on hydrophobic non top coat resists processes. Additionally, improvements to reduce micro bridging were evaluated. Finally bevel rinse hardware to prevent contamination of the immersion scanner was tested.

Random 65nm..45nm C/H printing using optimized illumination source and CD sizing by post processing

Printing random Contact Holes (C/H) is one of the most difficult tasks in current low-k1 lithography. Different approaches have been proposed and demonstrated successfully. One approach is the use of extensive Resolution Enhancement Technique such as sub-resolution assisting features, focus drilling and interference mapping lithography in combination with strong off-axis illumination. These techniques often lead to enhanced complexity at the OPC and mask making side. In order to keep the complexity low, soft illumination modes have been proposed like Soft-Annular (bullseye) and Soft-Quasar type illumination [1]. It has been shown that the minimum k1 for the latter route is k1=0.41 using experimental results up to 0.93 NA. In this paper we demonstrate that the latter route can be extended to 45nm C/H at a minimum pitch of 120nm when using 1.35 NA. In order to achieve this we additionally applied a CD sizing technique to create the very small C/H.

Investigation of processing performance and requirements for next generation lithography cluster tools

In this paper we summarize our investigations into processing capability on the CLEAN TRACKTM LITHIUS ProTM -i & TWINSCANTM NXT:1950i litho cluster. Process performance with regards to critical dimension (CD) uniformity and defectivity are investigated to confirm adherence to ITRS1 roadmaps specifications. Additionally, a study of wafer backside particle contamination is performed to understand the implications towards processing. As wafer stage chuck cleaning on the scanner will require considerable down time, this study is necessary to understand the requirements for manufacturability. Previous work from our collaboration succeeded in a processing improvement of over 80% in across wafer CD variation by implementing the newest post exposure bake (PEB) plate design2 and optimized developer process. With regards to defectivity, the use of the advanced defect reduction (ADR) process with an optimized bevel cut of the resist allowed the use of a high contact angle material process which is required for optimal immersion hood performance. In this work, further optimization of the process with consideration of the design concept of the TWINSCANTM NXT:1950i and hardware modifications on the CLEAN TRACKTM LITHIUS ProTM -i will be performed. From this investigation, it is expected to understand the process capability of 38nm CD uniformity using novel developer hardware. Additionally, the defectivity challenges for processing with higher scan speeds in combination with the hydrophobicity of the coating materials and edge cut strategy will be clarified. Initial evaluation results are analyzed to understand the correlation of various types and densities of contaminates on the backside of the wafer to the formation of wafer stage chuck focus spots (FS). Focus spots are a localized irregular focus and leveling height.

EUV processing investigation on state of the art coater/developer system

In order to further understand the processing sensitivities of the EUV resist process, TEL and imec have continued their collaborative efforts. For this work, TEL has delivered and installed the state of the art, CLEAN TRACK™ LITHIUS Pro™ -EUV coater/developer to the newly expanded imec 300mm cleanroom in Leuven, Belgium. The exposures detailed in this investigation were performed off-line to the ASML EUV Alpha Demo Tool (ADT) as well as on the inline ADT cluster with CLEAN TRACK™ ACT™ 12 coater/developer. As EUV feature sizes are reduced, is it apparent that there is a need for more precise processing control, as can be demonstrated in the LITHIUS Pro™ -EUV. In previous work from this collaboration1, initial investigations from the ACT™ 12 work showed reasonable results; however, certainly hardware and processing improvements are necessary for manufacturing quality processing performance. This work continues the investigation into CDU and defectivity performance, as well as improvements to the process with novel techniques such as advanced defect reduction (ADR), pattern collapse mitigation with FIRM™Extreme and resolution improvement with tetrabutylammoniumhydroxide (TBAH).