Hitoshi Uematsu

Implementation and experimental results of CLAD using SRTS method in ATM networks

Timing information must be transported through an ATM network when a CBR signal, whose timing is independent of that of the network, is transmitted as ATM cells. For this purpose, ITU-T Recommendation I.363 defines the SRTS (synchronous residual time stamp) method. The authors implement a DS-3 CLAD (cell assembly and disassembly) device using the SRTS method. The SRTS method generates jitter, which is similar to the destuff jitter experienced in a stuff multiplexing system. Amplitude and spectrum of the SRTS jitter are evaluated using the DS-3 CLAD device. Finally, high speed data transmission is conducted between FDDI-LANs, and high quality NTSC video transmission is achieved using the CLAD device in an ATM field trial.

Hardware-Based Precise Time Synchronization on Gb/s Ethernet Enhanced with Preemptive Priority

SUMMARY Time synchronization is indispensable for wide area distributed systems including sensor networks, automation systems, and measurement/control systems. Another application is clock distribution, which is indispensable to support continuous information transfer. Because of the increasing demand for more sophisticated applications, it is essential to establish a time synchronization technique that offers higher accuracy and reliability. Particularly, the accuracy of time synchronization for Ethernet must be enhanced since Ethernet is becoming more important in telecommunication networks. This paper investigates a precise time synchronization technique that supports Gb/s Ethernet. To obtain accurate time synchronization, delay variation in message transfer and processing must be minimized. For this purpose, the paper first describes the implementation of preemptive priority queuing, which decreases the message delay variation of Ethernet. Through experiments, it is shown that preemptive priority queuing effectively achieves very low delay variation. The paper then proposes a method to synchronize the time signal of a slave node to that of the master node. The proposed time synchronization method is performed in the lower protocol layer and implemented on FPGA-based hardware. The method achieves superior time accuracy through the low message transfer/processing delay variation provided by preemptive priority, lower layer execution, and hardware implementation. The effectiveness of the method is confirmed through experiments. The experiments show that the time variation achieved by the method is smaller than 0.1 µsec. This perfor

WDM optical packet transmission experiment over 235 km of installed fibers

100-GHz spaced 16-channel WDM optical packets generated by a super-structure-grating (SSG)-DBR laser were transmitted over 235 km of installed DSFs at the line rate of 2.48832 Gb/s and packet length of 2 kbytes.

Hardware-based precise time synchronization on Gb/s Ethernet

The accuracy and precision of time synchronization in Ethernet must be enhanced since Ethernet is becoming a critical component of telecommunication networks. This paper investigates a precise time synchronization technique that supports Gb/s Ethernet. To obtain accurate time synchronization, delay variation in message transfer and processing must be minimized. For this purpose, the paper first describes an implementation of preemptive priority queuing, which decreases the message delay variation of Ethernet. The paper then proposes a time synchronization method that is performed in the lower protocol layer and then describes its implementation on FPGA-based hardware. The proposed method achieves superior time accuracy and precision through the low message transfer/processing delay variation provided by preemptive priority, lower layer execution, and hardware implementation. The effectiveness of the method is confirmed through experiments.

A Web Access SHaping method to improve the performance of congested servers

This paper proposes WASH, a Web Access SHaping method, to realize overload-tolerant and highly accessible web sites. Due to the explosive spread of the Internet and emerging sophisticated web applications, servers will become the bottlenecks of the Web. WASH works as a reverse proxy with load balancing and improves the service quality of popular servers. WASH provides two innovative mechanisms: load control with active process limit and application-aware request scheduling. Comparative experiments against current load balancers demonstrate the following superiority of WASH in handling heavy congestion: a) WASH keeps the response time for single page display to below 5 seconds and b) WASH maximizes the throughput of completed page displays and sessions.

A High Speed Video/Audio Stream Splitter for 4K Digital-Cinema

This paper develops the requirements of a high speed video stream splitting device and introduces a suitable architecture. The device can generate ten streams from a 500 Mbps 4K-digital-cinema stream without any loss. 1,000 receiving clients can be supported by connecting the devices in a multistage manner. It will be a key device in achieving a digital-cinema-based theater network and creating a new cinema distribution environment. The prototype of the device is implemented and the basic performance is evaluated by experiments. The evaluation results clearly show that the device satisfies the requirements

WDM packet routing prototype incorporating a bandwidth allocation function

This paper describes a WDM packet routing prototype incorporating a dynamic bandwidth allocation function for the physical layer. The total bandwidth for 2.5-Gbit/s optical packets was divided into 16 WDM channels with the granularity of 78 Mbit/s and bandwidth allocation was controlled from an operation system.

Adaptive minimum filter that achieves precise time synchronization on IP networks

Time synchronization protocols, such as NTP (Network Time Protocol), are frequently used on IP (Internet protocol) networks. These protocols estimate the clock time offset by measuring the Round Trip Time (RTT). In this estimation, errors may occur by delay variation, which is included in the measured RTT values. To avoid this, a conventional minimum filter technique using a fixed sample size has been developed previously. For the conventional filter to work efficiently, it is necessary to select the appropriate number of samples from which the minimum value is selected, while considering the tradeoff between the filtering effect and synchronization stability. This paper investigates an alternate filter, called an adaptive minimum filter, which controls the number of samples depending on the variation of the RTT values. This filter achieves a sufficient filtering effect as well as superior clock control stability. A computer simulation is used to evaluate the time synchronization protocol that employs the adaptive minimum filter. The simulation results show that the synchronization protocol with the adaptive minimum filter achieves better time accuracy and stability than that with the conventional minimum filter.

SDH line-error detection method using reduced BIP

For STM-N transmission lines in a synchronous digital hierarchy (SDH), a 24N bits interleaved parity (BIP) detection code is established in order to monitor transmission line errors. the hardware required for BIP code calculation increases in proportion to the speed of the transmission line. For example, with STM-16 (2.48832 Gbit/s), the BIP code uses 384 bits, and the line-error detection function occupies a large portion of the SDH interface hardware. This paper proposes a method to solve the foregoing problem, which implements line-error detection by using a shorter BIP code obtained by conversion of the received BIP code, at the receiving end. At the transmitting end, BIP code conforming with the ITU-T (formerly CCITT) standard is generated. This method allows integration with international standards, without degrading performance. That is, with an STM-16, the hardware size is reduced by about 3000 gates, which is approximately a 20 percent reduction in the total gate count of an SDH processor.