Yoshiaki Yamada

Advanced resist process enabling implementation of CD controllability for 32 nm and beyond

Exposure wavelength has been changing dramatically as semiconductor design rules shrink, and for 32nm-node fine processes and beyond, it is predicted that the drop in optical contrast when using 193nm immersion lithography exposure technology will make it difficult to ensure good resolution performance in fine and dense resist patterns. To address this problem, studies have begun on extreme ultraviolet (EUV) lithography technology and double patterning technology that uses 193nm immersion lithography as alternative technologies, but many problems have been reported at the present stage of development. Against the above background, we investigated various process flows with the aim of reducing production processes and cost in double patterning technology that uses 193nm immersion lithography. We consequently developed an advanced process technique for use after 1st resist pattern formation and established a litho-litho-etch (LLE) process. The application of this technology decreases the number of total processes used in ordinary double patterning technology. In this paper, we focus on double patterning technology in 193nm immersion lithography and report on the performance of our original advanced process technique and on our evaluation of double patterning technology.

Enabling 35nm double patterning contact imaging using a novel CD shrink process

With 32nm and 22nm feature size node in the near future, Double patterning type processing will be in mainstream device manufacturing in most cutting edge Fabrication facilities. These type of processes requires cooperation between the litho cell and the other processing modules. In a collaboration between ASML and TEL we have developed a integrated solution to image 30nm Contacts. We describe a novel technique to achieve a geometric shrink from a starting geometry of 65nm down to the final feature size of 30nm for each of the two contact images Processing 2 images separately could produce two distinct populations for alignment and critical dimensions. We will show the ability to image 65nm contacts on a 130nm pitch with acceptable process windows and then apply the novel CD shrink process to shrink the 65nm contacts to 30nm final dimension. The second level of contacts is imaged in between the 1st set of contacts allowing us to image a 32nm ½ pitch contact pattern. We show the ability to Image 2 separate sets of contacts using a split clip layout with a single distribution for critical output parameters. We address the following process challenges: 1) Overlay capability across the slit and across the field. 2) Critical Dimension capability across the slit and across the Field. 3) Sidewall angle integrity with acceptable process window. Using the novel CD shrink process TEL has developed and imaging capability of the an ASML 1700i TWINSCAN, we can achieve a double pattern contact process with acceptable process capability.

Advanced ultraviolet cross-link process and materials for global planarization

The use of a conventional thermal cross-link materials such as negative resists, anti-reflective coating (BARC), and planarizing layers does not lead to excellent planarization for multilevel interconnects, and specially via arrays prior to trench patterning for an advance lithography. The large thicknesses bias between the blanket areas and interconnect areas, and between the blanket areas and via arrays are usually observed. This large thickness bias creates problems during next lithography by narrowing the process latitude. Recently, chemical mechanical polishing (CMP) technology has been proposed to achieve global planarization. However, the CMP planarization technique is very sensitive to pattern density, and chemical etching reaction had high possibility to increase the dielectric constant. The current CMP technique still requires a new investment in the CMP equipment. In this paper, we reported another novel approach for global planarization using UV cross-link material (XUVTM) and the dielectric ultra violet exposure unit in coater equipment (TOKYO ELECTRON LTD CLEAN TRACKTM). This planar technique provides benefits for reducing the thickness bias observed in the 22-65 nm generation lithography and imprint processes. Using this technique, a remarkable reduction in via topography with 1.1 μm as a depth and 0.9-1.0 μm as a diameter has been achieved excellent thickness bias less than 20 nm. And, the planarization of the film obtained from the XUVTM was very high as compared with that of the film obtained from thermal cross-link gap fill material as the reference, particularly under severe coating conditions such as dense patterns.