Ho Keun Song

Electrical Properties of the La2O3/4H-SiC Interface Prepared by Atomic Layer Deposition Using La(iPrCp)3 and H2O

The La2O3 and Al2O3/La2O3 layers were grown on 4H-SiC by atomic layer deposition (ALD) method. The electrical properties of La2O3 on 4H-SiC were examined using metal-insulator-semiconductor (MIS) structures of Pt/La2O3(18nm)/4H-SiC and Pt/Al2O3(10nm)/La2O3(5nm)/4H-SiC. For the Pt/La2O3(18nm)/4H-SiC structure, even though the leakage current density was slightly reduced after the rapid thermal annealing at 500 oC, accumulation capacitance was gradually increased with increasing bias voltage due to a high leakage current. On the other hand, since the leakage current in the accumulation regime was decreased for the Pt/Al2O3/La2O3/4H-SiC MIS structure owing to the capped Al2O3 layer, the capacitance was saturated. But the saturation capacitance was strongly dependent on frequency, indicating a leaky interfacial layer formed between the La2O3 and SiC during the fabrication process of Pt/Al2O3(10nm)/ La2O3(5nm)/ 4H-SiC structure.

Homoepitaxial growth and electrical characterization of iron-doped semi-insulating 4H-SiC epilayer

The authors attempted to grow a semi-insulating silicon carbide (SiC) epitaxial layer by in situ iron doping. The homoepitaxial growth of the iron-doped 4H-SiC layer was performed by metal-organic chemical vapor deposition using the organo-silicon precursor bis(trimethylsilylmethane) (C7H20Si2) and the metal-organic precursor t-butylferrocene (C14H17Fe). For the measurement of the resistivity of the iron-doped 4H-SiC epilayers, the authors used the on resistance of Schottky barrier diode. Based on the measurement of the on resistance, it is shown that the free carrier concentration was decreased with increasing partial pressure of t-butylferrocene. The resistivity of the iron-doped 4H-SiC epilayer was about 108Ωcm.

Electrical Properties of Atomic-Layer-Deposited La2O3/Thermal-Nitrided SiO2 Stacking Dielectric on 4H-SiC(0001)

We have investigated the electrical properties of metal-oxide-semiconductor (MOS) capacitors with atomic-layer-deposited La2O3, thermal-nitrided SiO2, and atomic-layer-deposited La2O3/thermal-nitrided SiO2 on n-type 4H-SiC. A significant reduction in leakage current density has been observed in La2O3 structure when a 6-nm thick thermal nitrided SiO2 has been sandwiched between the La2O3 and SiC. However, this reduction is still considered high if compared to sample having thermal-nitrided SiO2 alone. The reasons for this have been explained in this paper.

Characterization of Undoped and Nitrogen-Doped 4H-SiC Thin Films by CVD from Bis(trimethylsilylmethane) Precursor

High-quality 4H-SiC epi layers were grown on 8 off-axis (0001) 4H-SiC substrates by chemical vapor deposition (CVD) using a single precursor, bis(trimethylsilylmethane) at a substrate temperature of 1380°C. The background doping level of the undoped epi layers was reduced by adjusting of the CVD chamber pressure and Si/C ratio. As the chamber pressure decreased from 360 to 180 Torr, the carrier concentration of the undoped epi layers decreased from 6.8 × 10 16 to 2.0 x 10 16 cm -3 . Moreover, CH 4 addition of 10 standard cubic centimeters per minute in the chamber at 180 Torr resulted in the reduction of the carrier concentration to 2 × 10 15 cm -3 , which can be explained by the well-known site-competition effect. The impurity incorporation effect on macrostep bunching was also discussed based on the strong correlation of atomic force microscopy topologies and impurity concentration. As the flow rate of nitrogen gas (N 2 ) increased, the electron concentration of the epi layers linearly increased. With variation of the N 2 flow rate, a total n-doping range from 2.0 × 10 17 to 1.0 X 10 21 cm -3 was achieved.

Effect of Postoxidation Annealing on High Temperature Grown SiO2 / 4H-SiC Interfaces

SiO 2 was grown by dry (O 2 ) thermal oxidation (at 1175, 1300, or 1400°C) on n-type 4H-SiC substrates. The samples were prepared by subsequently exposing the grown Si0 2 film on 4H-SiC to postoxidation annealing (POA) treatment using nitric oxide (NO) gas. The SiC-Si0 2 interfaces were characterized by high frequency capacitance-voltage measurements, X-ray photoelectron spectroscopy (XPS), and ellipsometry. The interface trap density of the dry oxide grown at 1300°C was much lower than others. At a higher grown temperature (1400°C), the electrical and physical properties of the oxide were not improved compared to those oxides grown at 1175°C. The XPS measurements provided evidence for the presence of intermediate oxidation states of Si oxycarbide in all samples. The areal densities of the intermediate oxidation states affected the interface trap density. The NO POA treatment significantly improved the interface trap density, the near-interface trap density, and the effective oxide charge density of the oxides grown at 1175 and 1300°C. But, this improvement was not observed for the oxide grown at 1400°C. The electrical properties of the metal-oxide-semiconductor devices fabricated using these oxides have also been discussed in terms of the oxide chemical compositions, which were determined by XPS and an oxide etching test.

Homoepitaxial Growth of Vanadium-Doped Semi-insulating 4H-SiC Using Bis-trimethylsilylmethane and Bis-cyclopentadienylvanadium Precursors

The authors attempted to grow a semi-insulating 4H-SiC epitaxial layer by in situ vanadium doping. The homoepitaxial growth of the vanadium-doped 4H-SiC layer was performed by metallorganic chemical vapor deposition using the organosilicon precursor bis-trimethylsilylmethane (BTMSM, C 7 H 20 Si 2 ) and the metallorganic precursor bis-cyclopentadienylvanadium (Verrocene, C 10 H 10 V). The vanadium doping effect on the crystallinity of the epi layer was very destructive. Vanadium-doped epi layers grown under normal conditions had various crystal defects such as micropipes and polytype inclusions, but this crystallinity degradation was overcome by elevating the growth temperature. For measurement of the resistivity of the highly resistive vanadium-doped 4H-SiC epi layers, the authors used the on-resistance technique. Based on the measurements of the on-resistance of the Schottky barrier diode fabricated using the vanadium-doped epi layers, it was revealed that the residual donor concentration of the epi layers was decreased with increasing partial pressure of verrocene. The resistivity of the in situ vanadium-doped 4H-SiC epi layer was about 10 7 -10 12 Ω cm.

4H-SiC Planar MESFETs on High-Purity Semi-Insulating Substrates

Planar MESFETs were fabricated on high-purity semi-insulating (HPSI) 4H-SiC substrates. The saturation drain current of the fabricated MESFETs with a gate length of 0.5 μm and a gate width of 100 μm was 430 mA/mm, and the transconductance was 25 mS/mm. The maximum oscillation frequency and cut-off frequency were 26.4 GHz and 7.2 GHz, respectively. The power gain was 8.4 dB and the maximum output power density was 2.8 W/mm for operation of class A at CW 2 GHz. MESFETs on HPSI substrates showed no current instability and much higher output power density in comparison to MESFETs on vanadium-doped SI substrates.

Effects of thermally oxidized-SiN gate oxide on 4H-SiC substrate

We have investigated and reported the results on oxidized-SiN gate oxides on n-type 4H-SiC. The quality of this oxide has been compared with thermal nitrided and dry oxides. In the oxidized-SiC sample, a significant improvement in oxide deposition/growth rate has been obtained while the metal-oxide-semiconductor characteristics of the oxide are comparable to the thermal-nitrided oxide and much better than dry oxide. This achievement has been explained using a proposed chemical model.

Fabrication and Characterization of 4H-SiC Planar MESFET Using Ion- Implantation

4H-SiC planar MESFETs having submicron-gate length were fabricated using ion-implantation and their DC and RF performances were characterized. The ion-implantation process which is essential to fabricate a planar device was investigated. Activation annealing after ion-implantation was performed in induction heating system under Ar atmosphere and the annealing condition was optimized. The fabricated MESFET showed good contact properties and pinch-off characteristics. The possibility of application of planar MESFETs in high voltage operation was suggested. Introduction SiC is expected to be an attractive candidate for the application of high-frequency and high-power devices due to its superior electrical, chemical and thermal properties. 4H-SiC MESFET, especially, has many advantages benefiting from the merits of 4H-SiC [1,2]. However, there is much to be desired in applying typical recess-etched gate structure to SiC because recess dry etching of the gate region degrades the Schottky characteristics [3]. To improve the device performances, planar MESFET having good ohmic and Schottky contact properties was fabricated without recess gate etching [4]. Ion-implantation was used as an essential process to fabricate a planar device [5]. In this work, 4H-SiC planar MESFETs having submicron-gate length were fabricated and the DC and RF performances were characterized. The surface morphology and electrical properties of ion-implanted region were investigated by AFM and Hall measurements. Experimental Fig. 1 shows the schematic cross-sectional structure and microscope image of a fabricated MESFET. The gate-to-source spacing, gate length and gate-to-drain spacing were 1.5 μm, 0.5 μm and 2.0 μm, respectively. The substrate was an n-type 4H-SiC purchased from Cree, Inc., with a lightly doped, 5 μm-thick p-type buffer layer and a 0.2 μm-thick n-type channel layer doped at 1.9 × 10 cm. The fabrication process included mesa isolation, ion-implantation and activation anneal, field oxide formation, ohmic contact formation, gate definition, and pad metallization. The cleaning of substrate was performed very carefully before each procedure. Mesa isolation was performed by reactive ion etching (RIE) using a SiO2 mask. To form highly doped source and drain regions, high-temperature and multiple-energy ion-implantation with phosphorous was carried out. Induction heating system was used to activate the implanted ions. All metals were deposited by e-beam evaporation. Evaporated Ni obtained using post-deposition annealing (PDA) at 1000oC for 2 min in Ar atmosphere was used for ohmic contacts. Gate contact was formed using Ni followed by the deposition of Pt Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 1181-1184 doi:10.4028/www.scientific.net/MSF.457-460.1181

Observation of stacking faults formed during homoepitaxial growth of p-type 4H-SiC

Threading dislocations and their transformation into stacking faults (SFs) are observed in p-type 4H-SiC epitaxial layers by high voltage transmission electron microscope. Homoepitaxial growth and in situ aluminum doping of 4H-SiC epitaxial layers are carried out using the organosilicon precursor bistrimethylsilylmethane (C7H20Si2 and the metal-organic precursor trimethylaluminum (C3H9Al), and the free hole concentration of the most heavily aluminum-doped epitaxial layers is >1021 cm−3. Threading dislocations are formed at the interface between the epitaxial layer and the substrate. However, the density of these threading dislocations decreases toward the epitaxial layer surface with their transformations to SFs.