Hoon Joo Na

Electrical Properties of the La2O3/4H-SiC Interface Prepared by Atomic Layer Deposition Using La(iPrCp)3 and H2O

The La2O3 and Al2O3/La2O3 layers were grown on 4H-SiC by atomic layer deposition (ALD) method. The electrical properties of La2O3 on 4H-SiC were examined using metal-insulator-semiconductor (MIS) structures of Pt/La2O3(18nm)/4H-SiC and Pt/Al2O3(10nm)/La2O3(5nm)/4H-SiC. For the Pt/La2O3(18nm)/4H-SiC structure, even though the leakage current density was slightly reduced after the rapid thermal annealing at 500 oC, accumulation capacitance was gradually increased with increasing bias voltage due to a high leakage current. On the other hand, since the leakage current in the accumulation regime was decreased for the Pt/Al2O3/La2O3/4H-SiC MIS structure owing to the capped Al2O3 layer, the capacitance was saturated. But the saturation capacitance was strongly dependent on frequency, indicating a leaky interfacial layer formed between the La2O3 and SiC during the fabrication process of Pt/Al2O3(10nm)/ La2O3(5nm)/ 4H-SiC structure.

Electrical Properties of Atomic-Layer-Deposited La2O3/Thermal-Nitrided SiO2 Stacking Dielectric on 4H-SiC(0001)

We have investigated the electrical properties of metal-oxide-semiconductor (MOS) capacitors with atomic-layer-deposited La2O3, thermal-nitrided SiO2, and atomic-layer-deposited La2O3/thermal-nitrided SiO2 on n-type 4H-SiC. A significant reduction in leakage current density has been observed in La2O3 structure when a 6-nm thick thermal nitrided SiO2 has been sandwiched between the La2O3 and SiC. However, this reduction is still considered high if compared to sample having thermal-nitrided SiO2 alone. The reasons for this have been explained in this paper.

Characterization of Undoped and Nitrogen-Doped 4H-SiC Thin Films by CVD from Bis(trimethylsilylmethane) Precursor

High-quality 4H-SiC epi layers were grown on 8 off-axis (0001) 4H-SiC substrates by chemical vapor deposition (CVD) using a single precursor, bis(trimethylsilylmethane) at a substrate temperature of 1380°C. The background doping level of the undoped epi layers was reduced by adjusting of the CVD chamber pressure and Si/C ratio. As the chamber pressure decreased from 360 to 180 Torr, the carrier concentration of the undoped epi layers decreased from 6.8 × 10 16 to 2.0 x 10 16 cm -3 . Moreover, CH 4 addition of 10 standard cubic centimeters per minute in the chamber at 180 Torr resulted in the reduction of the carrier concentration to 2 × 10 15 cm -3 , which can be explained by the well-known site-competition effect. The impurity incorporation effect on macrostep bunching was also discussed based on the strong correlation of atomic force microscopy topologies and impurity concentration. As the flow rate of nitrogen gas (N 2 ) increased, the electron concentration of the epi layers linearly increased. With variation of the N 2 flow rate, a total n-doping range from 2.0 × 10 17 to 1.0 X 10 21 cm -3 was achieved.

Effect of annealing on electrical properties of Pt/β-SiC contact

Abstract The property of contacts on semiconductors, which are deposited and annealed in high temperatures, is significantly affected by the annealing condition. SiC is one of the most attractive semiconductors applied in high temperature devices. In this study, the possibility of Pt being used as Schottky contact on SiC was examined by investigating the effects of annealing on the electrical properties of Pt/β-SiC contact. The as-deposited Pt/n-type β-SiC contacts showed ohmic property, which is attributed to the donor-like traps at the interface due to the sputtering damage. On the other hand, after annealing the contacts showed Schottky property, which seems to be originated from the annealing of traps and the movement of the junction into the defect-free SiC film during annealing. The barrier height increased with increasing annealing temperature, showing 1.37 eV at the annealing temperature of 900°C.

Morphological and structural characteristics of homoepitaxial 4H-SiC thin films by chemical vapor deposition using bis-trimethylsilylmethane precursor

High quality 4H-SiC monocrystalline films were homoepitaxially grown on 8.0° off-oriented (0001) 4H-SiC at a low temperature (1643 K) by metal-organic chemical vapor deposition (MOCVD). The correlation between the structural properties of the films and the growth parameters, in particular, the substrate temperature, and the flow rate of source material BTMSM, was investigated to elucidate the possible benefits of a single precursor on low-temperature thin film growth. The films were examined by optical microscopy, scanning electron microscopy (SEM), triple crystal X-ray diffractometry (TCD), and photoluminescence. Reciprocal space mapping results of the (0004) Bragg spot showed that the full width at half maximum (FWHM) of the rocking curve of the epilayer grown at 1643 K was 9.3 arcsec, which is extremely low as compared with the lowest value reported (13 arcsec). The high film quality was confirmed by low-temperature photoluminescence. The homoepitaxial growth condition for high quality monocrystalline 4H-SiC was also suggested in terms of the growth temperature and supersaturation of the source material.

4H-SiC Planar MESFETs on High-Purity Semi-Insulating Substrates

Planar MESFETs were fabricated on high-purity semi-insulating (HPSI) 4H-SiC substrates. The saturation drain current of the fabricated MESFETs with a gate length of 0.5 μm and a gate width of 100 μm was 430 mA/mm, and the transconductance was 25 mS/mm. The maximum oscillation frequency and cut-off frequency were 26.4 GHz and 7.2 GHz, respectively. The power gain was 8.4 dB and the maximum output power density was 2.8 W/mm for operation of class A at CW 2 GHz. MESFETs on HPSI substrates showed no current instability and much higher output power density in comparison to MESFETs on vanadium-doped SI substrates.

Fabrication and Characterization of 4H-SiC Planar MESFET Using Ion- Implantation

4H-SiC planar MESFETs having submicron-gate length were fabricated using ion-implantation and their DC and RF performances were characterized. The ion-implantation process which is essential to fabricate a planar device was investigated. Activation annealing after ion-implantation was performed in induction heating system under Ar atmosphere and the annealing condition was optimized. The fabricated MESFET showed good contact properties and pinch-off characteristics. The possibility of application of planar MESFETs in high voltage operation was suggested. Introduction SiC is expected to be an attractive candidate for the application of high-frequency and high-power devices due to its superior electrical, chemical and thermal properties. 4H-SiC MESFET, especially, has many advantages benefiting from the merits of 4H-SiC [1,2]. However, there is much to be desired in applying typical recess-etched gate structure to SiC because recess dry etching of the gate region degrades the Schottky characteristics [3]. To improve the device performances, planar MESFET having good ohmic and Schottky contact properties was fabricated without recess gate etching [4]. Ion-implantation was used as an essential process to fabricate a planar device [5]. In this work, 4H-SiC planar MESFETs having submicron-gate length were fabricated and the DC and RF performances were characterized. The surface morphology and electrical properties of ion-implanted region were investigated by AFM and Hall measurements. Experimental Fig. 1 shows the schematic cross-sectional structure and microscope image of a fabricated MESFET. The gate-to-source spacing, gate length and gate-to-drain spacing were 1.5 μm, 0.5 μm and 2.0 μm, respectively. The substrate was an n-type 4H-SiC purchased from Cree, Inc., with a lightly doped, 5 μm-thick p-type buffer layer and a 0.2 μm-thick n-type channel layer doped at 1.9 × 10 cm. The fabrication process included mesa isolation, ion-implantation and activation anneal, field oxide formation, ohmic contact formation, gate definition, and pad metallization. The cleaning of substrate was performed very carefully before each procedure. Mesa isolation was performed by reactive ion etching (RIE) using a SiO2 mask. To form highly doped source and drain regions, high-temperature and multiple-energy ion-implantation with phosphorous was carried out. Induction heating system was used to activate the implanted ions. All metals were deposited by e-beam evaporation. Evaporated Ni obtained using post-deposition annealing (PDA) at 1000oC for 2 min in Ar atmosphere was used for ohmic contacts. Gate contact was formed using Ni followed by the deposition of Pt Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 1181-1184 doi:10.4028/www.scientific.net/MSF.457-460.1181

Fabrication of 4H-SiC Planar MESFETs on High-Purity Semi-insulating Substrates

4H-SiC planar MESFETs were fabricated using ion-implantation on high-purity semi-insulating substrate, and their DC and RF performances were characterized. A modified RCA method was used to clean the substrate before each procedure. Sacrificial oxide was grown after channel layer etching to eliminate plasma damage to the gate region. A thin, thermal oxide layer was grown to passivate the surface and then a thick field oxide was deposited by CVD. The maximum oscillation frequency of 26.4 GHz and the cut-off frequency of 7.2 GHz were obtained. The power gain was 8.4 dB and the output power was 2.8 W/mm at 2 GHz.

Improvements in the Reverse Characteristics of 4H-SiC Schottky Barrier Diodes by Hydrogen Treatments

We fabricated 4H-SiC Schottky barrier diodes with various metals such as titanium, nickel and platinum. Density of interface states Dit and neutral level φo (which is the position that the Fermi level must assume if the surface is electrically neutral) were calculated 1.8×10 12 cm -2 eV -1 and 1.76 eV, respectively. In order to reduce reverse leakage current, hydrogen annealing and hydrogen plasma treatment were performed after Schottky contact metallization. The reverse leakage current measured at -100 V was reduced by one or two order of magnitude. An improvement of reverse leakage current was observed in case of both hydrogen annealing and hydrogen plasma treatment.

Homoepitaxial Growth of Vanadium-Doped 4H-SiC Using Bis-Trimethylsilylmethane and Verrocene Precursors

The authors attempted to grow a semi-insulating SiC epitaxial layer by in-situ vanadium doping. The homoepitaxial growth of the vanadium-doped 4H-SiC layer was performed by MOCVD using the organo-silicon precursor, bis-trimethylsilylmethane (BTMSM, [C7H20Si2]) and the metal-organic precursor, bis-cyclopentadienylvanadium (Verrocene, [C10H10V]). Vanadium doping effect on crystallinity of epilayer was very destructive. Vanadium-doped epilayers grown on normal condition had various surface or crystal defects such as micropipes, polytype inclusions. But this crystallinity degradation was overcome by high growth temperature. For the measurement of the resistivity of the highly resistive vanadium-doped 4H-SiC epilayers, the authors used the on-resistance technique. Based on the measurements of the on-resistance of the epilayers using the current-voltage technique, it is shown that the residual donor concentration of the epilayers was decreased with increasing partial pressure of verrocene. The resistivity of the vanadium-doped 4H-SiC epilayer was about 107 /cm.