Ho Yang

One-Dimensional Soft-Demapping Algorithms for Rotated QAM and Software Implementation on DSP

To improve detection performance of quadrature amplitude modulation (QAM), signal space diversity (SSD) has been exploited and adopted for the second generation of digital video broadcasting (DVB-T2) system. Maximum-likelihood detection (MLD) to get full SSD is avoided because of enormous computational complexity. Its max-log approximated detection (full search algorithm) and subregion based soft-demappers are also too complex to be implemented due to their two-dimensional (2D) Euclidean distance calculation. In particular, the complexity becomes the main burden for the software implementation, which is attractive for multistandard broadcasting receivers. To tackle the main bottleneck, we propose one-dimensional (1D) soft-demappers. By reformulating a rotated QAM signal as two layered pulse amplitude modulation (PAM) signals, the full search algorithm is simplified to an MMSE decorrelation followed by 1D soft-demapping, where Gaussian approximation is used for the interferences. Additional interference cancellation is considered to further suppress its residual interference. For 256-QAM with 4/5 code rate in memoryless Rayleigh channels with/without erasures, the performance gap to the full search is within 0.15 dB at 10-3 bit error rate (BER), while the complexity is less than 8%. Due to the significant complexity reduction of the proposed algorithms, the software implementation of a DVB-T2 receiver on DSP is feasible with 73% less computations than the one with the full-search-based soft-demapper.

Software-defined DVT-T2 demodulator using scalable DSP processors

This paper describes the feasibility of software-defined demodulator of DVB-T2 standard using the scalable DSP processor. This paper focuses mainly on the DVB-T2 receiver design and implementation of four major software blocks of the demodulator: FFTs, channel estimator, multi-level de-interleavers and rotated QAM soft-demapper. In particular, 2K-point FFT function is analyzed and mapped on the scalable architecture of coarse-grained reconfigurable array (CGRA) processors resulting 51dB signal to quantization noise ratio (SQNR) performance. The computational burden of frequency interpolator and frequency/cell deinterleavers are greatly reduced with specially designed intrinsics, 30% and 85%, respectively, from the original implementation. The softdemapper for rotated QAM constellation becomes feasible with the latest 1D-MMSE decorrelation method though it is still the most expensive function covering 40% of DTG106 mode. By implementing full chain demodulation software including abovementioned four major functions, it is demonstrated that the software-defined DVB-T2 demodulator is realizable with software on two scalable CGRA processors running at 300MHz.

Software-defined DVB-T2 receiver using coarse-grained reconfigurable array processors

This paper describes the feasibility of software implementation of DVB-T2 receiver with DTG-106 [1] mode using the coarse-grained reconfigurable array (CGRA) based processor. This paper focuses mainly on DVB-T2 system design and implementation of major software functions of DVB-T2 demodulator: FFT, frequency interpolation, multi-level de-interleaving, and soft-demapper. By implementing the full chain DVB-T2 software and measuring the cycle performance, we demonstrate the software implantation of DVB-T2 on dual core CGRA processor running at 400MHz.

Progressive equalizer matrix calculation using QR decomposition in MIMO-OFDM systems

Multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) technology has become a promising solution in current wireless communication systems. However, the implementation of MIMO-OFDM systems imposes a heavy complexity burden of equalizer matrix calculation on the training symbols due to the strict processing delay requirement. This paper presents a progressive QRD based equalizer matrix calculation method, which can significantly reduce the computational complexity in the last training symbol by distributing the heavy equalizer matrix calculation over multiple training symbols. Our proposed method was verified in the IEEE 802.11ac systems which has tough latency constraint. For 4 × 4 antenna configurations, the computational complexity on the last training symbol can be reduced by up to 75% without any BER loss.

√M-best candidates based soft-demapper for rotated M-QAM constellation

In the second generation terrestrial digital video broadcasting (DVB-T2) systems, one of the important features is the rotated quadrature amplitude modulation (QAM) with cyclic Q delay exploiting signal space diversity to improve detection performance. However, the complexity of soft-demapper is increased, because it needs to calculate the Euclidean distances between the received signal and all candidate points, and then to find the minimums for log-likelihood ratio (LLR) calculation. In this paper, we propose a reduced complexity soft-demapper that selects only √M-best candidates for LLR calculation of either even or odd bits. The candidate set is formed by selecting the closest points to the image made by projecting the received signal onto the constellation grid lines. In total, it only calculates the Euclidean distances for 2√M points, which hence can reduce the complexity significantly. In spite of the reduced complexity, the √M-best candidate set is optimal because it always includes the minimum-distance point in the original full set. Finally, our results show that the proposed soft-demapper achieves the same bit error rate (BER) performance as the Max-Log based full search one, but the complexity is reduced by 67.5% and 85.9%, respectively for 64-QAM and 256-QAM cases.

Software-based giga-bit WLAN platform

The design of baseband processor usually requires hardware and software co-design because of the partitioned functions over the ASIC hardware and DSPs. The portion of DSP is recently increasing as the computing power of DSP is sufficient to run the most baseband algorithms. In the paper, we deal with software-defined WLAN modem of IEEE 802.11ac covering most functions of baseband with DSP software. The receiver software is designed for the in-house DSP core that has 3 vector function units with 512-bit SIMD instructions running at 1GHz clock. To show the feasibility of 1Gbit/sec WLAN platform, we first utilize the SystemC simulation, and then implement the RTL and relevant software for the digital only baseband on the FPGA testbed. The SystemC simulation is 100 times faster than RTL simulation, to verify the full functionality of the baseband by presenting the text data transfer at 1.3Kbit/sec. We also demonstrate a video streaming of 20Mbit/sec on the FPGA testbed running at 20MHz by down-scaling the signal processing speed by the factor of 1/50.

Scalable radio processor architecture for modern wireless communications

In this paper, we propose an architecture of scalable radio processor targeting an OFDM based wireless modem. The architecture is based on the coarse-grained reconfigurable array (CGRA), which provides programmable and flexible accelerators by reconfiguring hardware resources at run time. On the other hand, the architecture maximizes the data parallelism by implementing 32-way SEVTD operations. Other features considered in the current implementation include mini-core structure, dedicated vector memory, and simplified datapath. The proposed architecture is compared to the precedent 4×4 CGRA processor, and evaluated with several communication kernels in terms of cycle, area and power. The implementation result shows that the proposed architecture has 3.6 times better in cycle performance with 2 times better scheduling but with double area penalty, resulting in 1495 cycles for complex 2K-FFT, to the best of our knowledge, that is the best DSP cycles reported until today. The synthesized results with 32nm library also show that the proposed architecture is operational at 800MHz, which is capable of running maximum 128 GOPS of wireless applications.

Software design of giga-bit WLAN on coarse grained reconfigurable array processors

In this paper, we present a software-defined radio (SDR) implementation of the 4×4 MIMO-OFDM baseband receivers on a coarse-grained reconfigurable array (CGRA) processor operating at 1 GHz clock for IEEE 802.11ac, which can support over 1Gbps data rate. However, software implementation of 802.11ac is very challenging because of the increasing computational complexity supporting giga-bit data transmission up to 6.9Gbps. For the software implementation, we focus on two major design issues: the software optimization for CGRA processors and the solution design for the preamble latency requirement. By measuring the computational cycles on the CGRA processor, we show the feasibility of SDR implementation for the 4×4 MIMO receiver of the 802.11ac. The BER is also evaluated to confirm the robustness of fixed point implementation.

DSP implementation of sqrt(M)-Best rotated QAM soft-demapper

In the second generation terrestrial digital video broadcasting (DVB-T2) systems, one of the important features is the usage of rotated quadrature amplitude modulation (QAM) to exploit signal space diversity. However, the implementation of soft-demapper is very challenging and becomes more complex as the modulation order increases. Recently, a √(M)-best soft-demapper was proposed which can achieve the same performance as the full search scheme but with low complexity. In this paper, we implement the √(M)-best soft-demapper on a digital signal processer (DSP) with a coarse-grained reconfigurable array (CGRA) architecture. The best candidate selection algorithm is accordingly modified for friendly implementation. Our results show that the √(M)-best soft-demapper can be implemented with 82% less cycles than the full search based soft-demapper for the most complex 256-QAM case.

A simple transmit beamforming technique by beam identification based on the energy detected at the receiver

In this paper transmit beamforming based on direction estimation is considered to enhance the reliability of data transmission. For the transmit beam design, we propose the simple beam design based on the direction-of-departure (DOD) to avoid the high computational angle estimation techniques. The proposed beam design technique approximates the wireless channels by selecting one dominant steering vector for the transmit beamformer. To minimize the feedback data, only the index of the best beam is fed back to the transmitter. Orthogonal codes are utilized to differentiate the largest energy beam from the others at the receiver side. The proposed scheme is thus applicable to both the rich scattering and line-of-sight (LOS) environments. The hybrid scheme is also discussed as the solution when the estimated beam is not acceptable for the beamforming.