Young-Hwan Park

System-level power-performance trade-offs in bus matrix communication architecture synthesis

System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customization of such architectures for an application requires the exploration of a large design space. Thus designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper we present an automated framework for fast system-level, application-specific, power- performance trade-offs in bus matrix communication architecture synthesis. Our paper makes two specific contributions. First, we develop energy macro-models for system-level exploration of bus matrix communication architectures. Second, we incorporate these macro- models into a bus matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different bus matrix configurations. Experimental results show that our energy macro- models incur less than 5% average absolute error compared to gate-level models. Furthermore, our bus matrix synthesis framework generates a tradeoff space with designs that exhibits an approximately 20% variation in power and 40% variation in performance on an industrial networking MPSoC application, demonstrating the utility of our approach.

System-Level SRAM Yield Enhancement

It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or SOC. Thus yield management of these SRAMs plays a crucial role in insuring design success. This paper demonstrates analysis techniques to model and improve the yield of SRAMs at the system level by proper accounting for the coupling between the algorithms targeted for an SOC and the performance, power, and yield of SRAMs used in implementing the algorithms. It is shown that coupling the algorithm and SRAM design phases provides significant advantages over independent optimization

A Multi-Granularity Power Modeling Methodology for Embedded Processors

With power becoming a major constraint for multiprocessor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is critical for these processor power models to be useable across various modeling abstractions in an electronic system level (ESL) design flow, to guide early design decisions. In this paper, we propose a unified processor power modeling methodology for the creation of power models at multiple granularity levels that can be quickly mapped to an ESL design flow. Our experimental results based on applying the proposed methodology on the OpenRISC and MIPS processors demonstrate the usefulness of having multiple power models. The generated models range from very high-level two-state and architectural/instruction set simulator models that can be used in transaction level models, to extremely detailed cycle-accurate models that enable early exploration of power optimization techniques. These models offer a designer tremendous flexibility to trade off estimation accuracy with estimation/simulation effort.

CAPPS: A Framework for Power–Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis

On-chip communication architectures have a significant impact on the power consumption and performance of emerging chip multiprocessor (CMP) applications. However, customization of such architectures for an application requires the exploration of a large design space. Designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper, we present an automated framework for fast system-level, application-specific, power-performance tradeoffs in a bus matrix communication architecture synthesis (CAPPS). Our study makes two specific contributions. First, we develop energy models for system-level exploration of bus matrix communication architectures. Second, we incorporate these models into a bus matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different bus matrix configurations. Experimental results show that our energy macromodels incur less than 5% average cycle energy error across 180-65 nm technology libraries. Our early system-level power estimation approach also shows a significant speedup ranging from 1000 to 2000× when compared with detailed gate-level power estimation. Furthermore, on applying our synthesis framework to three industrial networking CMP applications, a tradeoff space that exhibits up to 20% variation in power and up to 40% variation in performance is generated, demonstrating the usefulness of our approach.

System level power estimation methodology with H.264 decoder prediction IP case study

This paper presents a methodology to generate a hierarchy of power models for power estimation of custom hardware IP blocks, enabling a trade-off between power estimation accuracy, modeling effort and estimation speed. Our power estimation approach enables several novel system-level explorations - such as observing the effect of clock gating, and the effects of tweaking application-level parameters on system power - with an estimation accuracy that is close to the gate-level. We implemented our methodology on an H.264 video decoder prediction IP case study, created power models, and evaluated the effects of varying design parameters (e.g., clock gating, IIP frame ratios, quantization), allowing rapid system-level power exploration of these design parameters.

Software-defined DVT-T2 demodulator using scalable DSP processors

This paper describes the feasibility of software-defined demodulator of DVB-T2 standard using the scalable DSP processor. This paper focuses mainly on the DVB-T2 receiver design and implementation of four major software blocks of the demodulator: FFTs, channel estimator, multi-level de-interleavers and rotated QAM soft-demapper. In particular, 2K-point FFT function is analyzed and mapped on the scalable architecture of coarse-grained reconfigurable array (CGRA) processors resulting 51dB signal to quantization noise ratio (SQNR) performance. The computational burden of frequency interpolator and frequency/cell deinterleavers are greatly reduced with specially designed intrinsics, 30% and 85%, respectively, from the original implementation. The softdemapper for rotated QAM constellation becomes feasible with the latest 1D-MMSE decorrelation method though it is still the most expensive function covering 40% of DTG106 mode. By implementing full chain demodulation software including abovementioned four major functions, it is demonstrated that the software-defined DVB-T2 demodulator is realizable with software on two scalable CGRA processors running at 300MHz.

Methodology for multi-granularity embedded processor power model generation for an ESL design flow

With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is critical for these processor power models to be useable across various modeling abstractions in an electronic system level (ESL) design flow, to guide early design decisions. In this paper, we propose a unified processor power modeling methodology for the creation of power models at multiple granularity levels that can be quickly mapped to an ESL design flow. Our experimental results based on applying the proposed methodology on an OpenRISC processor demonstrate the usefulness of having multiple power models. The generated models range from very high-level two-state and architectural/ISS models that can be used in transaction level models (TLM), to extremely detailed cycle-accurate models that enable early exploration of power optimization techniques. These models offer a designer tremendous flexibility to trade off estimation accuracy with estimation/simulation effort.

Software-defined DVB-T2 receiver using coarse-grained reconfigurable array processors

This paper describes the feasibility of software implementation of DVB-T2 receiver with DTG-106 [1] mode using the coarse-grained reconfigurable array (CGRA) based processor. This paper focuses mainly on DVB-T2 system design and implementation of major software functions of DVB-T2 demodulator: FFT, frequency interpolation, multi-level de-interleaving, and soft-demapper. By implementing the full chain DVB-T2 software and measuring the cycle performance, we demonstrate the software implantation of DVB-T2 on dual core CGRA processor running at 400MHz.

Design and analysis of low power image filters toward defect-resilient embedded memories for multimedia socs

In the foreseeable future, System-on-Chip design will suffer from the problem of low yield especially in embedded memories. This can be a critical problem in a multimedia application like H.264 since it needs a huge amount of embedded memory. Existing approaches to solve this problem are not feasible given the higher memory defect density rates in technologies below 90 nm. In this paper, we present a new defect-resilience technique which employs the directional image filter in order to recover data from corrupted embedded memory. According to the analysis based on simulation the proposed filter can greatly improve the visual quality of the defected H.264 video streams with errors in data memory reaching up to 1.0% memory BER (Bit Error Rate) with lower power consumption relative to conventional median filter. Therefore, the proposed method can be a good solution to overcome the problem of low yield in multimedia SoC memory without suffering from additional redundant memory overhead.

A 1/2.33-inch 14.6M 1.4μm-pixel backside-illuminated CMOS image sensor with floating diffusion boosting

As pixel sizes continue to scale down, backside-illuminated (BSI) technology has been recently adopted as a solution to improve pixel SNR performance [1,2]. In addition, as the application of image sensors widens from digital still cameras to digital camcorders, high-resolution and high-speed operation are required. This paper presents 1/2.33-inch 14.6Mpixel CMOS image sensor employing a 1.4μm BSI pixel architecture with a floating-diffusion (FD) boosting scheme that enables high SNR and high speed read-out.